utility.hh (5552:9437b71c6460) utility.hh (5568:d14250d688d2)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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41
42namespace AlphaISA
43{
44 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
45
46 inline bool
47 inUserMode(ThreadContext *tc)
48 {
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 32 unchanged lines hidden (view full) ---

41
42namespace AlphaISA
43{
44 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
45
46 inline bool
47 inUserMode(ThreadContext *tc)
48 {
49 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
49 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
50 }
51
52 inline bool
53 isCallerSaveIntegerRegister(unsigned int reg)
54 {
55 panic("register classification not implemented");
56 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
57 }

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51
52 inline bool
53 isCallerSaveIntegerRegister(unsigned int reg)
54 {
55 panic("register classification not implemented");
56 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
57 }

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