utility.hh (5549:ed9b39dce0aa) | utility.hh (5552:9437b71c6460) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36#include "arch/alpha/types.hh" 37#include "arch/alpha/isa_traits.hh" 38#include "arch/alpha/regfile.hh" 39#include "base/misc.hh" 40#include "cpu/thread_context.hh" 41 42namespace AlphaISA 43{ | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36#include "arch/alpha/types.hh" 37#include "arch/alpha/isa_traits.hh" 38#include "arch/alpha/regfile.hh" 39#include "base/misc.hh" 40#include "cpu/thread_context.hh" 41 42namespace AlphaISA 43{ |
44 | |
45 uint64_t getArgument(ThreadContext *tc, int number, bool fp); 46 47 inline bool 48 inUserMode(ThreadContext *tc) 49 { 50 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 51 } 52 | 44 uint64_t getArgument(ThreadContext *tc, int number, bool fp); 45 46 inline bool 47 inUserMode(ThreadContext *tc) 48 { 49 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 50 } 51 |
53 inline bool isCallerSaveIntegerRegister(unsigned int reg) { | 52 inline bool 53 isCallerSaveIntegerRegister(unsigned int reg) 54 { |
54 panic("register classification not implemented"); 55 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 56 } 57 | 55 panic("register classification not implemented"); 56 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 57 } 58 |
58 inline bool isCalleeSaveIntegerRegister(unsigned int reg) { | 59 inline bool 60 isCalleeSaveIntegerRegister(unsigned int reg) 61 { |
59 panic("register classification not implemented"); 60 return (reg >= 9 && reg <= 15); 61 } 62 | 62 panic("register classification not implemented"); 63 return (reg >= 9 && reg <= 15); 64 } 65 |
63 inline bool isCallerSaveFloatRegister(unsigned int reg) { | 66 inline bool 67 isCallerSaveFloatRegister(unsigned int reg) 68 { |
64 panic("register classification not implemented"); 65 return false; 66 } 67 | 69 panic("register classification not implemented"); 70 return false; 71 } 72 |
68 inline bool isCalleeSaveFloatRegister(unsigned int reg) { | 73 inline bool 74 isCalleeSaveFloatRegister(unsigned int reg) 75 { |
69 panic("register classification not implemented"); 70 return false; 71 } 72 | 76 panic("register classification not implemented"); 77 return false; 78 } 79 |
73 inline Addr alignAddress(const Addr &addr, 74 unsigned int nbytes) { | 80 inline Addr 81 alignAddress(const Addr &addr, unsigned int nbytes) 82 { |
75 return (addr & ~(nbytes - 1)); 76 } 77 78 // Instruction address compression hooks | 83 return (addr & ~(nbytes - 1)); 84 } 85 86 // Instruction address compression hooks |
79 inline Addr realPCToFetchPC(const Addr &addr) { | 87 inline Addr 88 realPCToFetchPC(const Addr &addr) 89 { |
80 return addr; 81 } 82 | 90 return addr; 91 } 92 |
83 inline Addr fetchPCToRealPC(const Addr &addr) { | 93 inline Addr 94 fetchPCToRealPC(const Addr &addr) 95 { |
84 return addr; 85 } 86 87 // the size of "fetched" instructions (not necessarily the size 88 // of real instructions for PISA) | 96 return addr; 97 } 98 99 // the size of "fetched" instructions (not necessarily the size 100 // of real instructions for PISA) |
89 inline size_t fetchInstSize() { | 101 inline size_t 102 fetchInstSize() 103 { |
90 return sizeof(MachInst); 91 } 92 | 104 return sizeof(MachInst); 105 } 106 |
93 inline MachInst makeRegisterCopy(int dest, int src) { | 107 inline MachInst 108 makeRegisterCopy(int dest, int src) 109 { |
94 panic("makeRegisterCopy not implemented"); 95 return 0; 96 } 97 98 // Machine operations | 110 panic("makeRegisterCopy not implemented"); 111 return 0; 112 } 113 114 // Machine operations |
115 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, int regnum); 116 void restoreMachineReg(RegFile ®s, const AnyReg ®, int regnum); |
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99 | 117 |
100 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 101 int regnum); 102 103 void restoreMachineReg(RegFile ®s, const AnyReg ®, 104 int regnum); 105 | |
106 /** 107 * Function to insure ISA semantics about 0 registers. 108 * @param tc The thread context. 109 */ 110 template <class TC> 111 void zeroRegisters(TC *tc); 112 113 // Alpha IPR register accessors 114 inline bool PcPAL(Addr addr) { return addr & 0x3; } | 118 /** 119 * Function to insure ISA semantics about 0 registers. 120 * @param tc The thread context. 121 */ 122 template <class TC> 123 void zeroRegisters(TC *tc); 124 125 // Alpha IPR register accessors 126 inline bool PcPAL(Addr addr) { return addr & 0x3; } |
115 inline void startupCPU(ThreadContext *tc, int cpuId) { 116 tc->activate(0); 117 } | 127 inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } |
118 119 //////////////////////////////////////////////////////////////////////// 120 // 121 // Translation stuff 122 // 123 124 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 125 --- 33 unchanged lines hidden --- | 128 129 //////////////////////////////////////////////////////////////////////// 130 // 131 // Translation stuff 132 // 133 134 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 135 --- 33 unchanged lines hidden --- |