utility.hh (4240:cde9d7751cce) utility.hh (4826:259b996a6da6)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37#include "arch/alpha/isa_traits.hh"
38#include "arch/alpha/regfile.hh"
39#include "base/misc.hh"
40#include "cpu/thread_context.hh"
41
42namespace AlphaISA
43{
44
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 28 unchanged lines hidden (view full) ---

37#include "arch/alpha/isa_traits.hh"
38#include "arch/alpha/regfile.hh"
39#include "base/misc.hh"
40#include "cpu/thread_context.hh"
41
42namespace AlphaISA
43{
44
45 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
46
45 static inline bool
46 inUserMode(ThreadContext *tc)
47 {
48 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
49 }
50
51 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
52 panic("register classification not implemented");

--- 104 unchanged lines hidden --- 		47 static inline bool
48 inUserMode(ThreadContext *tc)
49 {
50 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
51 }
52
53 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
54 panic("register classification not implemented");

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