utility.hh (4182:5b2c0d266107) utility.hh (4194:af4f6022394b)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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43{
44
45 static inline bool
46 inUserMode(ThreadContext *tc)
47 {
48 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
49 }
50
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 34 unchanged lines hidden (view full) ---

43{
44
45 static inline bool
46 inUserMode(ThreadContext *tc)
47 {
48 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
49 }
50
51 static inline ExtMachInst
52 makeExtMI(MachInst inst, Addr pc) {
53#if FULL_SYSTEM
54 ExtMachInst ext_inst = inst;
55 if (pc && 0x1)
56 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
57 else
58 return ext_inst;
59#else
60 return ExtMachInst(inst);
61#endif
62 }
63
51 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
52 panic("register classification not implemented");
53 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
54 }
55
56 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
57 panic("register classification not implemented");
58 return (reg >= 9 && reg <= 15);

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105 * Function to insure ISA semantics about 0 registers.
106 * @param tc The thread context.
107 */
108 template <class TC>
109 void zeroRegisters(TC *tc);
110
111 // Alpha IPR register accessors
112 inline bool PcPAL(Addr addr) { return addr & 0x3; }
64 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
65 panic("register classification not implemented");
66 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
67 }
68
69 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
70 panic("register classification not implemented");
71 return (reg >= 9 && reg <= 15);

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118 * Function to insure ISA semantics about 0 registers.
119 * @param tc The thread context.
120 */
121 template <class TC>
122 void zeroRegisters(TC *tc);
123
124 // Alpha IPR register accessors
125 inline bool PcPAL(Addr addr) { return addr & 0x3; }
126 inline void startupCPU(ThreadContext *tc, int cpuId) {
127 tc->activate(0);
128 }
113#if FULL_SYSTEM
114
115 ////////////////////////////////////////////////////////////////////////
116 //
117 // Translation stuff
118 //
119
120 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }

--- 33 unchanged lines hidden --- 		129#if FULL_SYSTEM
130
131 ////////////////////////////////////////////////////////////////////////
132 //
133 // Translation stuff
134 //
135
136 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }

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