utility.hh (4172:141705d83494) | utility.hh (4181:6edaeff44647) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 34 unchanged lines hidden (view full) --- 43{ 44 45 static inline bool 46 inUserMode(ThreadContext *tc) 47 { 48 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 49 } 50 | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 34 unchanged lines hidden (view full) --- 43{ 44 45 static inline bool 46 inUserMode(ThreadContext *tc) 47 { 48 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 49 } 50 |
51 static inline ExtMachInst 52 makeExtMI(MachInst inst, Addr pc) { | 51 enum PredecodeResult { 52 MoreBytes = 1, 53 ExtMIReady = 2 54 }; 55 56 static inline unsigned int 57 predecode(ExtMachInst & ext_inst, Addr pc, MachInst inst, ThreadContext *) { 58 ext_inst = inst; |
53#if FULL_SYSTEM | 59#if FULL_SYSTEM |
54 ExtMachInst ext_inst = inst; | |
55 if (pc && 0x1) | 60 if (pc && 0x1) |
56 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 57 else 58 return ext_inst; 59#else 60 return ExtMachInst(inst); | 61 ext_inst|=(static_cast |
61#endif | 62#endif |
63 return MoreBytes | ExtMIReady; |
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62 } 63 64 inline bool isCallerSaveIntegerRegister(unsigned int reg) { 65 panic("register classification not implemented"); 66 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 67 } 68 69 inline bool isCalleeSaveIntegerRegister(unsigned int reg) { --- 97 unchanged lines hidden --- | 64 } 65 66 inline bool isCallerSaveIntegerRegister(unsigned int reg) { 67 panic("register classification not implemented"); 68 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 69 } 70 71 inline bool isCalleeSaveIntegerRegister(unsigned int reg) { --- 97 unchanged lines hidden --- |