utility.hh (3961:42374ae36922) utility.hh (4172:141705d83494)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 31 unchanged lines hidden (view full) ---

40#include "cpu/thread_context.hh"
41
42namespace AlphaISA
43{
44
45 static inline bool
46 inUserMode(ThreadContext *tc)
47 {
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 31 unchanged lines hidden (view full) ---

40#include "cpu/thread_context.hh"
41
42namespace AlphaISA
43{
44
45 static inline bool
46 inUserMode(ThreadContext *tc)
47 {
48 return (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
48 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
49 }
50
51 static inline ExtMachInst
52 makeExtMI(MachInst inst, Addr pc) {
53#if FULL_SYSTEM
54 ExtMachInst ext_inst = inst;
55 if (pc && 0x1)
56 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);

--- 110 unchanged lines hidden --- 		49 }
50
51 static inline ExtMachInst
52 makeExtMI(MachInst inst, Addr pc) {
53#if FULL_SYSTEM
54 ExtMachInst ext_inst = inst;
55 if (pc && 0x1)
56 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);

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