1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 32#ifndef __ARCH_ALPHA_UTILITY_HH__ 33#define __ARCH_ALPHA_UTILITY_HH__ 34 |
35#include "arch/alpha/types.hh" 36#include "arch/alpha/isa_traits.hh" 37#include "arch/alpha/regfile.hh" 38#include "base/misc.hh" |
39#include "config/full_system.hh" |
40#include "cpu/thread_context.hh" 41 |
42namespace AlphaISA { |
43 |
44uint64_t getArgument(ThreadContext *tc, int number, bool fp); |
45 |
46inline bool 47inUserMode(ThreadContext *tc) 48{ 49 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 50} |
51 |
52inline bool 53isCallerSaveIntegerRegister(unsigned int reg) 54{ 55 panic("register classification not implemented"); 56 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 57} |
58 |
59inline bool 60isCalleeSaveIntegerRegister(unsigned int reg) 61{ 62 panic("register classification not implemented"); 63 return (reg >= 9 && reg <= 15); 64} |
65 |
66inline bool 67isCallerSaveFloatRegister(unsigned int reg) 68{ 69 panic("register classification not implemented"); 70 return false; 71} |
72 |
73inline bool 74isCalleeSaveFloatRegister(unsigned int reg) 75{ 76 panic("register classification not implemented"); 77 return false; 78} |
79 |
80inline Addr 81alignAddress(const Addr &addr, unsigned int nbytes) 82{ 83 return (addr & ~(nbytes - 1)); 84} |
85 |
86// Instruction address compression hooks 87inline Addr 88realPCToFetchPC(const Addr &addr) 89{ 90 return addr; 91} |
92 |
93inline Addr 94fetchPCToRealPC(const Addr &addr) 95{ 96 return addr; 97} |
98 |
99// the size of "fetched" instructions (not necessarily the size 100// of real instructions for PISA) 101inline size_t 102fetchInstSize() 103{ 104 return sizeof(MachInst); 105} |
106 |
107inline MachInst 108makeRegisterCopy(int dest, int src) 109{ 110 panic("makeRegisterCopy not implemented"); 111 return 0; 112} |
113 |
114// Machine operations 115void saveMachineReg(AnyReg &savereg, const RegFile ®_file, int regnum); 116void restoreMachineReg(RegFile ®s, const AnyReg ®, int regnum); |
117 |
118/** 119 * Function to insure ISA semantics about 0 registers. 120 * @param tc The thread context. 121 */ 122template <class TC> 123void zeroRegisters(TC *tc); |
124 |
125// Alpha IPR register accessors 126inline bool PcPAL(Addr addr) { return addr & 0x3; } 127inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } |
128 |
129//////////////////////////////////////////////////////////////////////// 130// 131// Translation stuff 132// |
133 |
134inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } |
135 |
136// User Virtual 137inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } |
138 |
139// Kernel Direct Mapped 140inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 141inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } |
142 |
143// Kernel Virtual 144inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } |
145 |
146inline Addr 147TruncPage(Addr addr) 148{ return addr & ~(PageBytes - 1); } |
149 |
150inline Addr 151RoundPage(Addr addr) 152{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 153 154void initIPRs(ThreadContext *tc, int cpuId); |
155#if FULL_SYSTEM |
156void initCPU(ThreadContext *tc, int cpuId); |
157 |
158/** 159 * Function to check for and process any interrupts. 160 * @param tc The thread context. 161 */ 162template 163void processInterrupts(TC *tc); |
164#endif 165 166} // namespace AlphaISA 167 |
168#endif // __ARCH_ALPHA_UTILITY_HH__ |