1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36#include "arch/alpha/types.hh" 37#include "arch/alpha/isa_traits.hh" 38#include "arch/alpha/regfile.hh" 39#include "base/misc.hh" 40#include "cpu/thread_context.hh" 41 42namespace AlphaISA 43{ |
44 uint64_t getArgument(ThreadContext *tc, int number, bool fp); 45 46 inline bool 47 inUserMode(ThreadContext *tc) 48 { 49 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 50 } 51 |
52 inline bool 53 isCallerSaveIntegerRegister(unsigned int reg) 54 { |
55 panic("register classification not implemented"); 56 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 57 } 58 |
59 inline bool 60 isCalleeSaveIntegerRegister(unsigned int reg) 61 { |
62 panic("register classification not implemented"); 63 return (reg >= 9 && reg <= 15); 64 } 65 |
66 inline bool 67 isCallerSaveFloatRegister(unsigned int reg) 68 { |
69 panic("register classification not implemented"); 70 return false; 71 } 72 |
73 inline bool 74 isCalleeSaveFloatRegister(unsigned int reg) 75 { |
76 panic("register classification not implemented"); 77 return false; 78 } 79 |
80 inline Addr 81 alignAddress(const Addr &addr, unsigned int nbytes) 82 { |
83 return (addr & ~(nbytes - 1)); 84 } 85 86 // Instruction address compression hooks |
87 inline Addr 88 realPCToFetchPC(const Addr &addr) 89 { |
90 return addr; 91 } 92 |
93 inline Addr 94 fetchPCToRealPC(const Addr &addr) 95 { |
96 return addr; 97 } 98 99 // the size of "fetched" instructions (not necessarily the size 100 // of real instructions for PISA) |
101 inline size_t 102 fetchInstSize() 103 { |
104 return sizeof(MachInst); 105 } 106 |
107 inline MachInst 108 makeRegisterCopy(int dest, int src) 109 { |
110 panic("makeRegisterCopy not implemented"); 111 return 0; 112 } 113 114 // Machine operations |
115 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, int regnum); 116 void restoreMachineReg(RegFile ®s, const AnyReg ®, int regnum); |
117 |
118 /** 119 * Function to insure ISA semantics about 0 registers. 120 * @param tc The thread context. 121 */ 122 template <class TC> 123 void zeroRegisters(TC *tc); 124 125 // Alpha IPR register accessors 126 inline bool PcPAL(Addr addr) { return addr & 0x3; } |
127 inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } |
128 129 //////////////////////////////////////////////////////////////////////// 130 // 131 // Translation stuff 132 // 133 134 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 135 --- 33 unchanged lines hidden --- |