1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 30 unchanged lines hidden (view full) --- 39#include "base/misc.hh" 40#include "cpu/thread_context.hh" 41 42namespace AlphaISA 43{ 44 45 uint64_t getArgument(ThreadContext *tc, int number, bool fp); 46 |
47 inline bool |
48 inUserMode(ThreadContext *tc) 49 { 50 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 51 } 52 53 inline bool isCallerSaveIntegerRegister(unsigned int reg) { 54 panic("register classification not implemented"); 55 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); --- 103 unchanged lines hidden --- |