1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 101 unchanged lines hidden (view full) --- 110 template <class TC> 111 void zeroRegisters(TC *tc); 112 113 // Alpha IPR register accessors 114 inline bool PcPAL(Addr addr) { return addr & 0x3; } 115 inline void startupCPU(ThreadContext *tc, int cpuId) { 116 tc->activate(0); 117 } |
118 119 //////////////////////////////////////////////////////////////////////// 120 // 121 // Translation stuff 122 // 123 124 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 125 --- 10 unchanged lines hidden (view full) --- 136 inline Addr 137 TruncPage(Addr addr) 138 { return addr & ~(PageBytes - 1); } 139 140 inline Addr 141 RoundPage(Addr addr) 142 { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 143 |
144 void initIPRs(ThreadContext *tc, int cpuId); |
145#if FULL_SYSTEM 146 void initCPU(ThreadContext *tc, int cpuId); |
147 148 /** 149 * Function to check for and process any interrupts. 150 * @param tc The thread context. 151 */ 152 template <class TC> 153 void processInterrupts(TC *tc); 154#endif 155 156} // namespace AlphaISA 157 158#endif |