35d34
< #include "config/full_system.hh"
39a39
> #include "config/full_system.hh"
42,44c42
< namespace AlphaISA
< {
< uint64_t getArgument(ThreadContext *tc, int number, bool fp);
---
> namespace AlphaISA {
46,50c44
< inline bool
< inUserMode(ThreadContext *tc)
< {
< return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
< }
---
> uint64_t getArgument(ThreadContext *tc, int number, bool fp);
52,57c46,50
< inline bool
< isCallerSaveIntegerRegister(unsigned int reg)
< {
< panic("register classification not implemented");
< return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
< }
---
> inline bool
> inUserMode(ThreadContext *tc)
> {
> return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
> }
59,64c52,57
< inline bool
< isCalleeSaveIntegerRegister(unsigned int reg)
< {
< panic("register classification not implemented");
< return (reg >= 9 && reg <= 15);
< }
---
> inline bool
> isCallerSaveIntegerRegister(unsigned int reg)
> {
> panic("register classification not implemented");
> return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
> }
66,71c59,64
< inline bool
< isCallerSaveFloatRegister(unsigned int reg)
< {
< panic("register classification not implemented");
< return false;
< }
---
> inline bool
> isCalleeSaveIntegerRegister(unsigned int reg)
> {
> panic("register classification not implemented");
> return (reg >= 9 && reg <= 15);
> }
73,78c66,71
< inline bool
< isCalleeSaveFloatRegister(unsigned int reg)
< {
< panic("register classification not implemented");
< return false;
< }
---
> inline bool
> isCallerSaveFloatRegister(unsigned int reg)
> {
> panic("register classification not implemented");
> return false;
> }
80,84c73,78
< inline Addr
< alignAddress(const Addr &addr, unsigned int nbytes)
< {
< return (addr & ~(nbytes - 1));
< }
---
> inline bool
> isCalleeSaveFloatRegister(unsigned int reg)
> {
> panic("register classification not implemented");
> return false;
> }
86,91c80,84
< // Instruction address compression hooks
< inline Addr
< realPCToFetchPC(const Addr &addr)
< {
< return addr;
< }
---
> inline Addr
> alignAddress(const Addr &addr, unsigned int nbytes)
> {
> return (addr & ~(nbytes - 1));
> }
93,97c86,91
< inline Addr
< fetchPCToRealPC(const Addr &addr)
< {
< return addr;
< }
---
> // Instruction address compression hooks
> inline Addr
> realPCToFetchPC(const Addr &addr)
> {
> return addr;
> }
99,105c93,97
< // the size of "fetched" instructions (not necessarily the size
< // of real instructions for PISA)
< inline size_t
< fetchInstSize()
< {
< return sizeof(MachInst);
< }
---
> inline Addr
> fetchPCToRealPC(const Addr &addr)
> {
> return addr;
> }
107,112c99,105
< inline MachInst
< makeRegisterCopy(int dest, int src)
< {
< panic("makeRegisterCopy not implemented");
< return 0;
< }
---
> // the size of "fetched" instructions (not necessarily the size
> // of real instructions for PISA)
> inline size_t
> fetchInstSize()
> {
> return sizeof(MachInst);
> }
114,116c107,112
< // Machine operations
< void saveMachineReg(AnyReg &savereg, const RegFile &reg_file, int regnum);
< void restoreMachineReg(RegFile &regs, const AnyReg &reg, int regnum);
---
> inline MachInst
> makeRegisterCopy(int dest, int src)
> {
> panic("makeRegisterCopy not implemented");
> return 0;
> }
118,123c114,116
< /**
< * Function to insure ISA semantics about 0 registers.
< * @param tc The thread context.
< */
< template <class TC>
< void zeroRegisters(TC *tc);
---
> // Machine operations
> void saveMachineReg(AnyReg &savereg, const RegFile &reg_file, int regnum);
> void restoreMachineReg(RegFile &regs, const AnyReg &reg, int regnum);
125,127c118,123
< // Alpha IPR register accessors
< inline bool PcPAL(Addr addr) { return addr & 0x3; }
< inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
---
> /**
> * Function to insure ISA semantics about 0 registers.
> * @param tc The thread context.
> */
> template <class TC>
> void zeroRegisters(TC *tc);
129,132c125,127
< ////////////////////////////////////////////////////////////////////////
< //
< // Translation stuff
< //
---
> // Alpha IPR register accessors
> inline bool PcPAL(Addr addr) { return addr & 0x3; }
> inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
134c129,132
< inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
---
> ////////////////////////////////////////////////////////////////////////
> //
> // Translation stuff
> //
136,137c134
< // User Virtual
< inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
---
> inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
139,141c136,137
< // Kernel Direct Mapped
< inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
< inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
---
> // User Virtual
> inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
143,144c139,141
< // Kernel Virtual
< inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
---
> // Kernel Direct Mapped
> inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
> inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
146,148c143,144
< inline Addr
< TruncPage(Addr addr)
< { return addr & ~(PageBytes - 1); }
---
> // Kernel Virtual
> inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
150,152c146,148
< inline Addr
< RoundPage(Addr addr)
< { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
---
> inline Addr
> TruncPage(Addr addr)
> { return addr & ~(PageBytes - 1); }
154c150,154
< void initIPRs(ThreadContext *tc, int cpuId);
---
> inline Addr
> RoundPage(Addr addr)
> { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
>
> void initIPRs(ThreadContext *tc, int cpuId);
156c156
< void initCPU(ThreadContext *tc, int cpuId);
---
> void initCPU(ThreadContext *tc, int cpuId);
158,163c158,163
< /**
< * Function to check for and process any interrupts.
< * @param tc The thread context.
< */
< template <class TC>
< void processInterrupts(TC *tc);
---
> /**
> * Function to check for and process any interrupts.
> * @param tc The thread context.
> */
> template <class TC>
> void processInterrupts(TC *tc);
168c168
< #endif
---
> #endif // __ARCH_ALPHA_UTILITY_HH__