1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 32#ifndef __ARCH_ALPHA_UTILITY_HH__ 33#define __ARCH_ALPHA_UTILITY_HH__ 34
| 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 32#ifndef __ARCH_ALPHA_UTILITY_HH__ 33#define __ARCH_ALPHA_UTILITY_HH__ 34
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35#include "config/full_system.hh"
| |
36#include "arch/alpha/types.hh" 37#include "arch/alpha/isa_traits.hh" 38#include "arch/alpha/regfile.hh" 39#include "base/misc.hh"
| 35#include "arch/alpha/types.hh" 36#include "arch/alpha/isa_traits.hh" 37#include "arch/alpha/regfile.hh" 38#include "base/misc.hh"
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| 39#include "config/full_system.hh"
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40#include "cpu/thread_context.hh" 41
| 40#include "cpu/thread_context.hh" 41
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42namespace AlphaISA 43{ 44 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
| 42namespace AlphaISA {
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45
| 43
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46 inline bool 47 inUserMode(ThreadContext *tc) 48 { 49 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 50 }
| 44uint64_t getArgument(ThreadContext *tc, int number, bool fp);
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51
| 45
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52 inline bool 53 isCallerSaveIntegerRegister(unsigned int reg) 54 { 55 panic("register classification not implemented"); 56 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 57 }
| 46inline bool 47inUserMode(ThreadContext *tc) 48{ 49 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 50}
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58
| 51
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59 inline bool 60 isCalleeSaveIntegerRegister(unsigned int reg) 61 { 62 panic("register classification not implemented"); 63 return (reg >= 9 && reg <= 15); 64 }
| 52inline bool 53isCallerSaveIntegerRegister(unsigned int reg) 54{ 55 panic("register classification not implemented"); 56 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 57}
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65
| 58
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66 inline bool 67 isCallerSaveFloatRegister(unsigned int reg) 68 { 69 panic("register classification not implemented"); 70 return false; 71 }
| 59inline bool 60isCalleeSaveIntegerRegister(unsigned int reg) 61{ 62 panic("register classification not implemented"); 63 return (reg >= 9 && reg <= 15); 64}
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72
| 65
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73 inline bool 74 isCalleeSaveFloatRegister(unsigned int reg) 75 { 76 panic("register classification not implemented"); 77 return false; 78 }
| 66inline bool 67isCallerSaveFloatRegister(unsigned int reg) 68{ 69 panic("register classification not implemented"); 70 return false; 71}
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79
| 72
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80 inline Addr 81 alignAddress(const Addr &addr, unsigned int nbytes) 82 { 83 return (addr & ~(nbytes - 1)); 84 }
| 73inline bool 74isCalleeSaveFloatRegister(unsigned int reg) 75{ 76 panic("register classification not implemented"); 77 return false; 78}
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85
| 79
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86 // Instruction address compression hooks 87 inline Addr 88 realPCToFetchPC(const Addr &addr) 89 { 90 return addr; 91 }
| 80inline Addr 81alignAddress(const Addr &addr, unsigned int nbytes) 82{ 83 return (addr & ~(nbytes - 1)); 84}
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92
| 85
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93 inline Addr 94 fetchPCToRealPC(const Addr &addr) 95 { 96 return addr; 97 }
| 86// Instruction address compression hooks 87inline Addr 88realPCToFetchPC(const Addr &addr) 89{ 90 return addr; 91}
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98
| 92
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99 // the size of "fetched" instructions (not necessarily the size 100 // of real instructions for PISA) 101 inline size_t 102 fetchInstSize() 103 { 104 return sizeof(MachInst); 105 }
| 93inline Addr 94fetchPCToRealPC(const Addr &addr) 95{ 96 return addr; 97}
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106
| 98
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107 inline MachInst 108 makeRegisterCopy(int dest, int src) 109 { 110 panic("makeRegisterCopy not implemented"); 111 return 0; 112 }
| 99// the size of "fetched" instructions (not necessarily the size 100// of real instructions for PISA) 101inline size_t 102fetchInstSize() 103{ 104 return sizeof(MachInst); 105}
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113
| 106
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114 // Machine operations 115 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, int regnum); 116 void restoreMachineReg(RegFile ®s, const AnyReg ®, int regnum);
| 107inline MachInst 108makeRegisterCopy(int dest, int src) 109{ 110 panic("makeRegisterCopy not implemented"); 111 return 0; 112}
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117
| 113
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118 /** 119 * Function to insure ISA semantics about 0 registers. 120 * @param tc The thread context. 121 */ 122 template <class TC> 123 void zeroRegisters(TC *tc);
| 114// Machine operations 115void saveMachineReg(AnyReg &savereg, const RegFile ®_file, int regnum); 116void restoreMachineReg(RegFile ®s, const AnyReg ®, int regnum);
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124
| 117
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125 // Alpha IPR register accessors 126 inline bool PcPAL(Addr addr) { return addr & 0x3; } 127 inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
| 118/** 119 * Function to insure ISA semantics about 0 registers. 120 * @param tc The thread context. 121 */ 122template <class TC> 123void zeroRegisters(TC *tc);
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128
| 124
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129 //////////////////////////////////////////////////////////////////////// 130 // 131 // Translation stuff 132 //
| 125// Alpha IPR register accessors 126inline bool PcPAL(Addr addr) { return addr & 0x3; } 127inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
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133
| 128
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134 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
| 129//////////////////////////////////////////////////////////////////////// 130// 131// Translation stuff 132//
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135
| 133
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136 // User Virtual 137 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
| 134inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
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138
| 135
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139 // Kernel Direct Mapped 140 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 141 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
| 136// User Virtual 137inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
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142
| 138
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143 // Kernel Virtual 144 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
| 139// Kernel Direct Mapped 140inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 141inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
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145
| 142
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146 inline Addr 147 TruncPage(Addr addr) 148 { return addr & ~(PageBytes - 1); }
| 143// Kernel Virtual 144inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
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149
| 145
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150 inline Addr 151 RoundPage(Addr addr) 152 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
| 146inline Addr 147TruncPage(Addr addr) 148{ return addr & ~(PageBytes - 1); }
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153
| 149
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154 void initIPRs(ThreadContext *tc, int cpuId);
| 150inline Addr 151RoundPage(Addr addr) 152{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 153 154void initIPRs(ThreadContext *tc, int cpuId);
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155#if FULL_SYSTEM
| 155#if FULL_SYSTEM
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156 void initCPU(ThreadContext *tc, int cpuId);
| 156void initCPU(ThreadContext *tc, int cpuId);
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157
| 157
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158 /** 159 * Function to check for and process any interrupts. 160 * @param tc The thread context. 161 */ 162 template <class TC> 163 void processInterrupts(TC *tc);
| 158/** 159 * Function to check for and process any interrupts. 160 * @param tc The thread context. 161 */ 162template 163void processInterrupts(TC *tc);
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164#endif 165 166} // namespace AlphaISA 167
| 164#endif 165 166} // namespace AlphaISA 167
|
168#endif
| 168#endif // __ARCH_ALPHA_UTILITY_HH__
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| |