1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 32#ifndef __ARCH_ALPHA_UTILITY_HH__ 33#define __ARCH_ALPHA_UTILITY_HH__ 34 35#include "config/full_system.hh" 36#include "arch/alpha/types.hh" 37#include "arch/alpha/isa_traits.hh" 38#include "arch/alpha/regfile.hh" 39#include "base/misc.hh" 40#include "cpu/thread_context.hh" 41 42namespace AlphaISA 43{
| 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 32#ifndef __ARCH_ALPHA_UTILITY_HH__ 33#define __ARCH_ALPHA_UTILITY_HH__ 34 35#include "config/full_system.hh" 36#include "arch/alpha/types.hh" 37#include "arch/alpha/isa_traits.hh" 38#include "arch/alpha/regfile.hh" 39#include "base/misc.hh" 40#include "cpu/thread_context.hh" 41 42namespace AlphaISA 43{
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44
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45 uint64_t getArgument(ThreadContext *tc, int number, bool fp); 46 47 inline bool 48 inUserMode(ThreadContext *tc) 49 { 50 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 51 } 52
| 44 uint64_t getArgument(ThreadContext *tc, int number, bool fp); 45 46 inline bool 47 inUserMode(ThreadContext *tc) 48 { 49 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 50 } 51
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53 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
| 52 inline bool 53 isCallerSaveIntegerRegister(unsigned int reg) 54 {
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54 panic("register classification not implemented"); 55 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 56 } 57
| 55 panic("register classification not implemented"); 56 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 57 } 58
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58 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
| 59 inline bool 60 isCalleeSaveIntegerRegister(unsigned int reg) 61 {
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59 panic("register classification not implemented"); 60 return (reg >= 9 && reg <= 15); 61 } 62
| 62 panic("register classification not implemented"); 63 return (reg >= 9 && reg <= 15); 64 } 65
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63 inline bool isCallerSaveFloatRegister(unsigned int reg) {
| 66 inline bool 67 isCallerSaveFloatRegister(unsigned int reg) 68 {
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64 panic("register classification not implemented"); 65 return false; 66 } 67
| 69 panic("register classification not implemented"); 70 return false; 71 } 72
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68 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
| 73 inline bool 74 isCalleeSaveFloatRegister(unsigned int reg) 75 {
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69 panic("register classification not implemented"); 70 return false; 71 } 72
| 76 panic("register classification not implemented"); 77 return false; 78 } 79
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73 inline Addr alignAddress(const Addr &addr, 74 unsigned int nbytes) {
| 80 inline Addr 81 alignAddress(const Addr &addr, unsigned int nbytes) 82 {
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75 return (addr & ~(nbytes - 1)); 76 } 77 78 // Instruction address compression hooks
| 83 return (addr & ~(nbytes - 1)); 84 } 85 86 // Instruction address compression hooks
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79 inline Addr realPCToFetchPC(const Addr &addr) {
| 87 inline Addr 88 realPCToFetchPC(const Addr &addr) 89 {
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80 return addr; 81 } 82
| 90 return addr; 91 } 92
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83 inline Addr fetchPCToRealPC(const Addr &addr) {
| 93 inline Addr 94 fetchPCToRealPC(const Addr &addr) 95 {
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84 return addr; 85 } 86 87 // the size of "fetched" instructions (not necessarily the size 88 // of real instructions for PISA)
| 96 return addr; 97 } 98 99 // the size of "fetched" instructions (not necessarily the size 100 // of real instructions for PISA)
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89 inline size_t fetchInstSize() {
| 101 inline size_t 102 fetchInstSize() 103 {
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90 return sizeof(MachInst); 91 } 92
| 104 return sizeof(MachInst); 105 } 106
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93 inline MachInst makeRegisterCopy(int dest, int src) {
| 107 inline MachInst 108 makeRegisterCopy(int dest, int src) 109 {
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94 panic("makeRegisterCopy not implemented"); 95 return 0; 96 } 97 98 // Machine operations
| 110 panic("makeRegisterCopy not implemented"); 111 return 0; 112 } 113 114 // Machine operations
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| 115 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, int regnum); 116 void restoreMachineReg(RegFile ®s, const AnyReg ®, int regnum);
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99
| 117
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100 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 101 int regnum); 102 103 void restoreMachineReg(RegFile ®s, const AnyReg ®, 104 int regnum); 105
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106 /** 107 * Function to insure ISA semantics about 0 registers. 108 * @param tc The thread context. 109 */ 110 template <class TC> 111 void zeroRegisters(TC *tc); 112 113 // Alpha IPR register accessors 114 inline bool PcPAL(Addr addr) { return addr & 0x3; }
| 118 /** 119 * Function to insure ISA semantics about 0 registers. 120 * @param tc The thread context. 121 */ 122 template <class TC> 123 void zeroRegisters(TC *tc); 124 125 // Alpha IPR register accessors 126 inline bool PcPAL(Addr addr) { return addr & 0x3; }
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115 inline void startupCPU(ThreadContext *tc, int cpuId) { 116 tc->activate(0); 117 }
| 127 inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
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118 119 //////////////////////////////////////////////////////////////////////// 120 // 121 // Translation stuff 122 // 123 124 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 125 126 // User Virtual 127 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 128 129 // Kernel Direct Mapped 130 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 131 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 132 133 // Kernel Virtual 134 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 135 136 inline Addr 137 TruncPage(Addr addr) 138 { return addr & ~(PageBytes - 1); } 139 140 inline Addr 141 RoundPage(Addr addr) 142 { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 143 144 void initIPRs(ThreadContext *tc, int cpuId); 145#if FULL_SYSTEM 146 void initCPU(ThreadContext *tc, int cpuId); 147 148 /** 149 * Function to check for and process any interrupts. 150 * @param tc The thread context. 151 */ 152 template <class TC> 153 void processInterrupts(TC *tc); 154#endif 155 156} // namespace AlphaISA 157 158#endif
| 128 129 //////////////////////////////////////////////////////////////////////// 130 // 131 // Translation stuff 132 // 133 134 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 135 136 // User Virtual 137 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 138 139 // Kernel Direct Mapped 140 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 141 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 142 143 // Kernel Virtual 144 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 145 146 inline Addr 147 TruncPage(Addr addr) 148 { return addr & ~(PageBytes - 1); } 149 150 inline Addr 151 RoundPage(Addr addr) 152 { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 153 154 void initIPRs(ThreadContext *tc, int cpuId); 155#if FULL_SYSTEM 156 void initCPU(ThreadContext *tc, int cpuId); 157 158 /** 159 * Function to check for and process any interrupts. 160 * @param tc The thread context. 161 */ 162 template <class TC> 163 void processInterrupts(TC *tc); 164#endif 165 166} // namespace AlphaISA 167 168#endif
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