1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 */
31
32#ifndef __ARCH_ALPHA_UTILITY_HH__
33#define __ARCH_ALPHA_UTILITY_HH__
34
35#include "config/full_system.hh"
36#include "arch/alpha/types.hh"
37#include "arch/alpha/isa_traits.hh"
38#include "arch/alpha/regfile.hh"
39#include "base/misc.hh"
40#include "cpu/thread_context.hh"
41
42namespace AlphaISA
43{
44
45 static inline ExtMachInst
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 */
31
32#ifndef __ARCH_ALPHA_UTILITY_HH__
33#define __ARCH_ALPHA_UTILITY_HH__
34
35#include "config/full_system.hh"
36#include "arch/alpha/types.hh"
37#include "arch/alpha/isa_traits.hh"
38#include "arch/alpha/regfile.hh"
39#include "base/misc.hh"
40#include "cpu/thread_context.hh"
41
42namespace AlphaISA
43{
44
45 static inline ExtMachInst
|
51 else
52 return ext_inst;
53#else
54 return ExtMachInst(inst);
55#endif
56 }
57
58 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
59 panic("register classification not implemented");
60 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
61 }
62
63 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
64 panic("register classification not implemented");
65 return (reg >= 9 && reg <= 15);
66 }
67
68 inline bool isCallerSaveFloatRegister(unsigned int reg) {
69 panic("register classification not implemented");
70 return false;
71 }
72
73 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
74 panic("register classification not implemented");
75 return false;
76 }
77
78 inline Addr alignAddress(const Addr &addr,
79 unsigned int nbytes) {
80 return (addr & ~(nbytes - 1));
81 }
82
83 // Instruction address compression hooks
84 inline Addr realPCToFetchPC(const Addr &addr) {
85 return addr;
86 }
87
88 inline Addr fetchPCToRealPC(const Addr &addr) {
89 return addr;
90 }
91
92 // the size of "fetched" instructions (not necessarily the size
93 // of real instructions for PISA)
94 inline size_t fetchInstSize() {
95 return sizeof(MachInst);
96 }
97
98 inline MachInst makeRegisterCopy(int dest, int src) {
99 panic("makeRegisterCopy not implemented");
100 return 0;
101 }
102
103 // Machine operations
104
105 void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
106 int regnum);
107
108 void restoreMachineReg(RegFile ®s, const AnyReg ®,
109 int regnum);
110
111 /**
112 * Function to insure ISA semantics about 0 registers.
113 * @param tc The thread context.
114 */
115 template <class TC>
116 void zeroRegisters(TC *tc);
117
118#if FULL_SYSTEM
119 // Alpha IPR register accessors
120 inline bool PcPAL(Addr addr) { return addr & 0x1; }
121
122 ////////////////////////////////////////////////////////////////////////
123 //
124 // Translation stuff
125 //
126
127 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
128
129 // User Virtual
130 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
131
132 // Kernel Direct Mapped
133 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
134 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
135
136 // Kernel Virtual
137 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
138
139 inline Addr
140 TruncPage(Addr addr)
141 { return addr & ~(PageBytes - 1); }
142
143 inline Addr
144 RoundPage(Addr addr)
145 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
146
147 void initCPU(ThreadContext *tc, int cpuId);
148 void initIPRs(ThreadContext *tc, int cpuId);
149
150 /**
151 * Function to check for and process any interrupts.
152 * @param tc The thread context.
153 */
154 template <class TC>
155 void processInterrupts(TC *tc);
156#endif
157
158} // namespace AlphaISA
159
160#endif
| 51 else
52 return ext_inst;
53#else
54 return ExtMachInst(inst);
55#endif
56 }
57
58 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
59 panic("register classification not implemented");
60 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
61 }
62
63 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
64 panic("register classification not implemented");
65 return (reg >= 9 && reg <= 15);
66 }
67
68 inline bool isCallerSaveFloatRegister(unsigned int reg) {
69 panic("register classification not implemented");
70 return false;
71 }
72
73 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
74 panic("register classification not implemented");
75 return false;
76 }
77
78 inline Addr alignAddress(const Addr &addr,
79 unsigned int nbytes) {
80 return (addr & ~(nbytes - 1));
81 }
82
83 // Instruction address compression hooks
84 inline Addr realPCToFetchPC(const Addr &addr) {
85 return addr;
86 }
87
88 inline Addr fetchPCToRealPC(const Addr &addr) {
89 return addr;
90 }
91
92 // the size of "fetched" instructions (not necessarily the size
93 // of real instructions for PISA)
94 inline size_t fetchInstSize() {
95 return sizeof(MachInst);
96 }
97
98 inline MachInst makeRegisterCopy(int dest, int src) {
99 panic("makeRegisterCopy not implemented");
100 return 0;
101 }
102
103 // Machine operations
104
105 void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
106 int regnum);
107
108 void restoreMachineReg(RegFile ®s, const AnyReg ®,
109 int regnum);
110
111 /**
112 * Function to insure ISA semantics about 0 registers.
113 * @param tc The thread context.
114 */
115 template <class TC>
116 void zeroRegisters(TC *tc);
117
118#if FULL_SYSTEM
119 // Alpha IPR register accessors
120 inline bool PcPAL(Addr addr) { return addr & 0x1; }
121
122 ////////////////////////////////////////////////////////////////////////
123 //
124 // Translation stuff
125 //
126
127 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
128
129 // User Virtual
130 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
131
132 // Kernel Direct Mapped
133 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
134 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
135
136 // Kernel Virtual
137 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
138
139 inline Addr
140 TruncPage(Addr addr)
141 { return addr & ~(PageBytes - 1); }
142
143 inline Addr
144 RoundPage(Addr addr)
145 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
146
147 void initCPU(ThreadContext *tc, int cpuId);
148 void initIPRs(ThreadContext *tc, int cpuId);
149
150 /**
151 * Function to check for and process any interrupts.
152 * @param tc The thread context.
153 */
154 template <class TC>
155 void processInterrupts(TC *tc);
156#endif
157
158} // namespace AlphaISA
159
160#endif
|