1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
27 */
28
29#ifndef __ARCH_ALPHA_UTILITY_HH__
30#define __ARCH_ALPHA_UTILITY_HH__
31
32#include "config/full_system.hh"
33#include "arch/alpha/types.hh"
34#include "arch/alpha/constants.hh"
35#include "arch/alpha/regfile.hh"
36#include "base/misc.hh"
37
38namespace AlphaISA
39{
40
41 static inline ExtMachInst
42 makeExtMI(MachInst inst, const uint64_t &pc) {
43#if FULL_SYSTEM
44 ExtMachInst ext_inst = inst;
45 if (pc && 0x1)
46 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
47 else
48 return ext_inst;
49#else
50 return ExtMachInst(inst);
51#endif
52 }
53
54 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
55 panic("register classification not implemented");
56 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
57 }
58
59 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
60 panic("register classification not implemented");
61 return (reg >= 9 && reg <= 15);
62 }
63
64 inline bool isCallerSaveFloatRegister(unsigned int reg) {
65 panic("register classification not implemented");
66 return false;
67 }
68
69 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
70 panic("register classification not implemented");
71 return false;
72 }
73
74 inline Addr alignAddress(const Addr &addr,
75 unsigned int nbytes) {
76 return (addr & ~(nbytes - 1));
77 }
78
79 // Instruction address compression hooks
80 inline Addr realPCToFetchPC(const Addr &addr) {
81 return addr;
82 }
83
84 inline Addr fetchPCToRealPC(const Addr &addr) {
85 return addr;
86 }
87
88 // the size of "fetched" instructions (not necessarily the size
89 // of real instructions for PISA)
90 inline size_t fetchInstSize() {
91 return sizeof(MachInst);
92 }
93
94 inline MachInst makeRegisterCopy(int dest, int src) {
95 panic("makeRegisterCopy not implemented");
96 return 0;
97 }
98
99 // Machine operations
100
101 void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
102 int regnum);
103
104 void restoreMachineReg(RegFile ®s, const AnyReg ®,
105 int regnum);
106
107 /**
108 * Function to insure ISA semantics about 0 registers.
109 * @param xc The execution context.
110 */
111 template <class XC>
112 void zeroRegisters(XC *xc);
113
114#if FULL_SYSTEM
115 // Alpha IPR register accessors
116 inline bool PcPAL(Addr addr) { return addr & 0x1; }
117
118 ////////////////////////////////////////////////////////////////////////
119 //
120 // Translation stuff
121 //
122
123 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
124
125 // User Virtual
126 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
127
128 // Kernel Direct Mapped
129 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
130 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
131
132 // Kernel Virtual
133 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
134
135 inline Addr
136 TruncPage(Addr addr)
137 { return addr & ~(PageBytes - 1); }
138
139 inline Addr
140 RoundPage(Addr addr)
141 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
142
143 void initCPU(ExecContext *xc, int cpuId);
144 void initIPRs(ExecContext *xc, int cpuId);
145
146 /**
147 * Function to check for and process any interrupts.
148 * @param xc The execution context.
149 */
150 template <class XC>
151 void processInterrupts(XC *xc);
152#endif
153
154} // namespace AlphaISA
155
156#endif
| 30 */
31
32#ifndef __ARCH_ALPHA_UTILITY_HH__
33#define __ARCH_ALPHA_UTILITY_HH__
34
35#include "config/full_system.hh"
36#include "arch/alpha/types.hh"
37#include "arch/alpha/constants.hh"
38#include "arch/alpha/regfile.hh"
39#include "base/misc.hh"
40
41namespace AlphaISA
42{
43
44 static inline ExtMachInst
45 makeExtMI(MachInst inst, const uint64_t &pc) {
46#if FULL_SYSTEM
47 ExtMachInst ext_inst = inst;
48 if (pc && 0x1)
49 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
50 else
51 return ext_inst;
52#else
53 return ExtMachInst(inst);
54#endif
55 }
56
57 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
58 panic("register classification not implemented");
59 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
60 }
61
62 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
63 panic("register classification not implemented");
64 return (reg >= 9 && reg <= 15);
65 }
66
67 inline bool isCallerSaveFloatRegister(unsigned int reg) {
68 panic("register classification not implemented");
69 return false;
70 }
71
72 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
73 panic("register classification not implemented");
74 return false;
75 }
76
77 inline Addr alignAddress(const Addr &addr,
78 unsigned int nbytes) {
79 return (addr & ~(nbytes - 1));
80 }
81
82 // Instruction address compression hooks
83 inline Addr realPCToFetchPC(const Addr &addr) {
84 return addr;
85 }
86
87 inline Addr fetchPCToRealPC(const Addr &addr) {
88 return addr;
89 }
90
91 // the size of "fetched" instructions (not necessarily the size
92 // of real instructions for PISA)
93 inline size_t fetchInstSize() {
94 return sizeof(MachInst);
95 }
96
97 inline MachInst makeRegisterCopy(int dest, int src) {
98 panic("makeRegisterCopy not implemented");
99 return 0;
100 }
101
102 // Machine operations
103
104 void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
105 int regnum);
106
107 void restoreMachineReg(RegFile ®s, const AnyReg ®,
108 int regnum);
109
110 /**
111 * Function to insure ISA semantics about 0 registers.
112 * @param xc The execution context.
113 */
114 template <class XC>
115 void zeroRegisters(XC *xc);
116
117#if FULL_SYSTEM
118 // Alpha IPR register accessors
119 inline bool PcPAL(Addr addr) { return addr & 0x1; }
120
121 ////////////////////////////////////////////////////////////////////////
122 //
123 // Translation stuff
124 //
125
126 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
127
128 // User Virtual
129 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
130
131 // Kernel Direct Mapped
132 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
133 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
134
135 // Kernel Virtual
136 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
137
138 inline Addr
139 TruncPage(Addr addr)
140 { return addr & ~(PageBytes - 1); }
141
142 inline Addr
143 RoundPage(Addr addr)
144 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
145
146 void initCPU(ExecContext *xc, int cpuId);
147 void initIPRs(ExecContext *xc, int cpuId);
148
149 /**
150 * Function to check for and process any interrupts.
151 * @param xc The execution context.
152 */
153 template <class XC>
154 void processInterrupts(XC *xc);
155#endif
156
157} // namespace AlphaISA
158
159#endif
|