1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 */
31
32#ifndef __ARCH_ALPHA_UTILITY_HH__
33#define __ARCH_ALPHA_UTILITY_HH__
34
35#include "config/full_system.hh"
36#include "arch/alpha/types.hh"
37#include "arch/alpha/isa_traits.hh"
38#include "arch/alpha/regfile.hh"
39#include "base/misc.hh"
40#include "cpu/thread_context.hh"
41
42namespace AlphaISA
43{
44
45 static inline bool
46 inUserMode(ThreadContext *tc)
47 {
48 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
49 }
50
51 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
52 panic("register classification not implemented");
53 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
54 }
55
56 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
57 panic("register classification not implemented");
58 return (reg >= 9 && reg <= 15);
59 }
60
61 inline bool isCallerSaveFloatRegister(unsigned int reg) {
62 panic("register classification not implemented");
63 return false;
64 }
65
66 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
67 panic("register classification not implemented");
68 return false;
69 }
70
71 inline Addr alignAddress(const Addr &addr,
72 unsigned int nbytes) {
73 return (addr & ~(nbytes - 1));
74 }
75
76 // Instruction address compression hooks
77 inline Addr realPCToFetchPC(const Addr &addr) {
78 return addr;
79 }
80
81 inline Addr fetchPCToRealPC(const Addr &addr) {
82 return addr;
83 }
84
85 // the size of "fetched" instructions (not necessarily the size
86 // of real instructions for PISA)
87 inline size_t fetchInstSize() {
88 return sizeof(MachInst);
89 }
90
91 inline MachInst makeRegisterCopy(int dest, int src) {
92 panic("makeRegisterCopy not implemented");
93 return 0;
94 }
95
96 // Machine operations
97
98 void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
99 int regnum);
100
101 void restoreMachineReg(RegFile &regs, const AnyReg &reg,
102 int regnum);
103
104 /**
105 * Function to insure ISA semantics about 0 registers.
106 * @param tc The thread context.
107 */
108 template <class TC>
109 void zeroRegisters(TC *tc);
110
111 // Alpha IPR register accessors
112 inline bool PcPAL(Addr addr) { return addr & 0x3; }
113 inline void startupCPU(ThreadContext *tc, int cpuId) {
114 tc->activate(0);
115 }
116#if FULL_SYSTEM
117
118 ////////////////////////////////////////////////////////////////////////
119 //
120 // Translation stuff
121 //
122
123 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
124
125 // User Virtual
126 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
127
128 // Kernel Direct Mapped
129 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
130 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
131
132 // Kernel Virtual
133 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
134
135 inline Addr
136 TruncPage(Addr addr)
137 { return addr & ~(PageBytes - 1); }
138
139 inline Addr
140 RoundPage(Addr addr)
141 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
142
143 void initCPU(ThreadContext *tc, int cpuId);
144 void initIPRs(ThreadContext *tc, int cpuId);
145
146 /**
147 * Function to check for and process any interrupts.
148 * @param tc The thread context.
149 */
150 template <class TC>
151 void processInterrupts(TC *tc);
152#endif
153
154} // namespace AlphaISA
155
156#endif