1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "arch/alpha/types.hh"
37#include "arch/alpha/isa_traits.hh"
38#include "arch/alpha/regfile.hh"
39#include "base/misc.hh"
40#include "cpu/thread_context.hh"
41
42namespace AlphaISA
43{
44
45 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
46
47 inline bool
48 inUserMode(ThreadContext *tc)
49 {
50 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
51 }
52
53 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
54 panic("register classification not implemented");
55 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
56 }
57
58 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
59 panic("register classification not implemented");
60 return (reg >= 9 && reg <= 15);
61 }
62
63 inline bool isCallerSaveFloatRegister(unsigned int reg) {
64 panic("register classification not implemented");
65 return false;
66 }
67
68 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
69 panic("register classification not implemented");
70 return false;
71 }
72
73 inline Addr alignAddress(const Addr &addr,
74 unsigned int nbytes) {
75 return (addr & ~(nbytes - 1));
76 }
77
78 // Instruction address compression hooks
79 inline Addr realPCToFetchPC(const Addr &addr) {
80 return addr;
81 }
82
83 inline Addr fetchPCToRealPC(const Addr &addr) {
84 return addr;
85 }
86
87 // the size of "fetched" instructions (not necessarily the size
88 // of real instructions for PISA)
89 inline size_t fetchInstSize() {
90 return sizeof(MachInst);
91 }
92
93 inline MachInst makeRegisterCopy(int dest, int src) {
94 panic("makeRegisterCopy not implemented");
95 return 0;
96 }
97
98 // Machine operations
99
100 void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
101 int regnum);
102
103 void restoreMachineReg(RegFile &regs, const AnyReg &reg,
104 int regnum);
105
106 /**
107 * Function to insure ISA semantics about 0 registers.
108 * @param tc The thread context.
109 */
110 template <class TC>
111 void zeroRegisters(TC *tc);
112
113 // Alpha IPR register accessors
114 inline bool PcPAL(Addr addr) { return addr & 0x3; }
115 inline void startupCPU(ThreadContext *tc, int cpuId) {
116 tc->activate(0);
117 }
118
119 ////////////////////////////////////////////////////////////////////////
120 //
121 // Translation stuff
122 //
123
124 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
125

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