1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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110 template <class TC>
111 void zeroRegisters(TC *tc);
112
113 // Alpha IPR register accessors
114 inline bool PcPAL(Addr addr) { return addr & 0x3; }
115 inline void startupCPU(ThreadContext *tc, int cpuId) {
116 tc->activate(0);
117 }
118#if FULL_SYSTEM
119
120 ////////////////////////////////////////////////////////////////////////
121 //
122 // Translation stuff
123 //
124
125 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
126

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137 inline Addr
138 TruncPage(Addr addr)
139 { return addr & ~(PageBytes - 1); }
140
141 inline Addr
142 RoundPage(Addr addr)
143 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
144
145 void initCPU(ThreadContext *tc, int cpuId);
146 void initIPRs(ThreadContext *tc, int cpuId);
147
148 /**
149 * Function to check for and process any interrupts.
150 * @param tc The thread context.
151 */
152 template <class TC>
153 void processInterrupts(TC *tc);
154#endif
155
156} // namespace AlphaISA
157
158#endif