1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 */
31
32#ifndef __ARCH_ALPHA_UTILITY_HH__
33#define __ARCH_ALPHA_UTILITY_HH__
34
35#include "arch/alpha/isa_traits.hh"
36#include "arch/alpha/registers.hh"
37#include "arch/alpha/types.hh"
38#include "base/misc.hh"
39#include "cpu/static_inst.hh"
40#include "cpu/thread_context.hh"
41#include "arch/alpha/ev5.hh"
42
43namespace AlphaISA {
44
45inline PCState
46buildRetPC(const PCState &curPC, const PCState &callPC)
47{
48 PCState retPC = callPC;
49 retPC.advance();
50 return retPC;
51}
52
53uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
54
55inline bool
56inUserMode(ThreadContext *tc)
57{
58 return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
59}
60
61/**
62 * Function to insure ISA semantics about 0 registers.
63 * @param tc The thread context.
64 */
65template <class TC>
66void zeroRegisters(TC *tc);
67
68// Alpha IPR register accessors
69inline bool PcPAL(Addr addr) { return addr & 0x3; }
70inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); }
71
72////////////////////////////////////////////////////////////////////////
73//
74// Translation stuff
75//
76
77inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
78
79// User Virtual
80inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
81
82// Kernel Direct Mapped
83inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
84inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
85
86// Kernel Virtual
87inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
88
89inline Addr
90TruncPage(Addr addr)
91{ return addr & ~(PageBytes - 1); }
92
93inline Addr
94RoundPage(Addr addr)
95{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
96
97void initIPRs(ThreadContext *tc, int cpuId);
98void initCPU(ThreadContext *tc, int cpuId);
99
100void copyRegs(ThreadContext *src, ThreadContext *dest);
101
102void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
103
104void skipFunction(ThreadContext *tc);
105
106inline void
107advancePC(PCState &pc, const StaticInstPtr inst)
108{
109 pc.advance();
110}
111
112inline uint64_t
113getExecutingAsid(ThreadContext *tc)
114{
115 return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
116}
117
118} // namespace AlphaISA
119
120#endif // __ARCH_ALPHA_UTILITY_HH__