1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 */
31
32#ifndef __ARCH_ALPHA_UTILITY_HH__
33#define __ARCH_ALPHA_UTILITY_HH__
34
35#include "config/full_system.hh"
36#include "arch/alpha/types.hh"
37#include "arch/alpha/isa_traits.hh"
38#include "arch/alpha/regfile.hh"
39#include "base/misc.hh"
40#include "cpu/thread_context.hh"
41
42namespace AlphaISA
43{
44
45 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
46
47 static inline bool
48 inUserMode(ThreadContext *tc)
49 {
50 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
51 }
52
53 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
54 panic("register classification not implemented");
55 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
56 }
57
58 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
59 panic("register classification not implemented");
60 return (reg >= 9 && reg <= 15);
61 }
62
63 inline bool isCallerSaveFloatRegister(unsigned int reg) {
64 panic("register classification not implemented");
65 return false;
66 }
67
68 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
69 panic("register classification not implemented");
70 return false;
71 }
72
73 inline Addr alignAddress(const Addr &addr,
74 unsigned int nbytes) {
75 return (addr & ~(nbytes - 1));
76 }
77
78 // Instruction address compression hooks
79 inline Addr realPCToFetchPC(const Addr &addr) {
80 return addr;
81 }
82
83 inline Addr fetchPCToRealPC(const Addr &addr) {
84 return addr;
85 }
86
87 // the size of "fetched" instructions (not necessarily the size
88 // of real instructions for PISA)
89 inline size_t fetchInstSize() {
90 return sizeof(MachInst);
91 }
92
93 inline MachInst makeRegisterCopy(int dest, int src) {
94 panic("makeRegisterCopy not implemented");
95 return 0;
96 }
97
98 // Machine operations
99
100 void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
101 int regnum);
102
103 void restoreMachineReg(RegFile &regs, const AnyReg &reg,
104 int regnum);
105
106 /**
107 * Function to insure ISA semantics about 0 registers.
108 * @param tc The thread context.
109 */
110 template <class TC>
111 void zeroRegisters(TC *tc);
112
113 // Alpha IPR register accessors
114 inline bool PcPAL(Addr addr) { return addr & 0x3; }
115 inline void startupCPU(ThreadContext *tc, int cpuId) {
116 tc->activate(0);
117 }
118#if FULL_SYSTEM
119
120 ////////////////////////////////////////////////////////////////////////
121 //
122 // Translation stuff
123 //
124
125 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
126
127 // User Virtual
128 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
129
130 // Kernel Direct Mapped
131 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
132 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
133
134 // Kernel Virtual
135 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
136
137 inline Addr
138 TruncPage(Addr addr)
139 { return addr & ~(PageBytes - 1); }
140
141 inline Addr
142 RoundPage(Addr addr)
143 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
144
145 void initCPU(ThreadContext *tc, int cpuId);
146 void initIPRs(ThreadContext *tc, int cpuId);
147
148 /**
149 * Function to check for and process any interrupts.
150 * @param tc The thread context.
151 */
152 template <class TC>
153 void processInterrupts(TC *tc);
154#endif
155
156} // namespace AlphaISA
157
158#endif