1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34
35#include "arch/alpha/isa_traits.hh"
36#include "arch/alpha/registers.hh"
37#include "arch/alpha/types.hh"
38#include "base/misc.hh"
39#include "config/full_system.hh"
40#include "cpu/static_inst.hh"
41#include "cpu/thread_context.hh"
42#include "arch/alpha/ev5.hh"
43
44namespace AlphaISA {
45
46inline PCState
47buildRetPC(const PCState &curPC, const PCState &callPC)
48{
49 PCState retPC = callPC;
50 retPC.advance();

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107void skipFunction(ThreadContext *tc);
108
109inline void
110advancePC(PCState &pc, const StaticInstPtr inst)
111{
112 pc.advance();
113}
114
115inline uint64_t
116getExecutingAsid(ThreadContext *tc)
117{
118 return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
119}
120
121} // namespace AlphaISA
122
123#endif // __ARCH_ALPHA_UTILITY_HH__