utility.cc (6330:786136379872) | utility.cc (7693:f1db1000d957) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 26 unchanged lines hidden (view full) --- 35#if FULL_SYSTEM 36#include "arch/alpha/vtophys.hh" 37#include "mem/vport.hh" 38#endif 39 40namespace AlphaISA { 41 42uint64_t | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 26 unchanged lines hidden (view full) --- 35#if FULL_SYSTEM 36#include "arch/alpha/vtophys.hh" 37#include "mem/vport.hh" 38#endif 39 40namespace AlphaISA { 41 42uint64_t |
43getArgument(ThreadContext *tc, int number, bool fp) | 43getArgument(ThreadContext *tc, int &number, uint8_t size, bool fp) |
44{ 45#if FULL_SYSTEM 46 const int NumArgumentRegs = 6; 47 if (number < NumArgumentRegs) { 48 if (fp) 49 return tc->readFloatRegBits(16 + number); 50 else 51 return tc->readIntReg(16 + number); --- 39 unchanged lines hidden (view full) --- 91 dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, 92 src->readMiscRegNoEffect(MISCREG_LOCKFLAG)); 93 dest->setMiscRegNoEffect(MISCREG_LOCKADDR, 94 src->readMiscRegNoEffect(MISCREG_LOCKADDR)); 95 96 copyIprs(src, dest); 97} 98 | 44{ 45#if FULL_SYSTEM 46 const int NumArgumentRegs = 6; 47 if (number < NumArgumentRegs) { 48 if (fp) 49 return tc->readFloatRegBits(16 + number); 50 else 51 return tc->readIntReg(16 + number); --- 39 unchanged lines hidden (view full) --- 91 dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, 92 src->readMiscRegNoEffect(MISCREG_LOCKFLAG)); 93 dest->setMiscRegNoEffect(MISCREG_LOCKADDR, 94 src->readMiscRegNoEffect(MISCREG_LOCKADDR)); 95 96 copyIprs(src, dest); 97} 98 |
99void 100skipFunction(ThreadContext *tc) 101{ 102 Addr newpc = tc->readIntReg(ReturnAddressReg); 103 tc->setPC(newpc); 104 tc->setNextPC(tc->readPC() + sizeof(TheISA::MachInst)); 105} 106 107 |
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99} // namespace AlphaISA 100 | 108} // namespace AlphaISA 109 |