1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Ali Saidi
30 */
31
32#include "arch/alpha/utility.hh"
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34#include "arch/alpha/vtophys.hh"
35#include "mem/fs_translating_port_proxy.hh"
36#include "sim/full_system.hh"
37
38namespace AlphaISA {
39
40uint64_t
41getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
42{
43 if (!FullSystem) {
44 panic("getArgument() is Full system only\n");
45 M5_DUMMY_RETURN;
46 }
47
48 const int NumArgumentRegs = 6;
49 if (number < NumArgumentRegs) {
50 if (fp)
51 return tc->readFloatRegBits(16 + number);
52 else
53 return tc->readIntReg(16 + number);
54 } else {
55 Addr sp = tc->readIntReg(StackPointerReg);
56 FSTranslatingPortProxy &vp = tc->getVirtProxy();
57 uint64_t arg = vp.read<uint64_t>(sp +
58 (number-NumArgumentRegs) *
59 sizeof(uint64_t));
60 return arg;
61 }
62}
63
64void
65copyRegs(ThreadContext *src, ThreadContext *dest)
66{
67 // First loop through the integer registers.
68 for (int i = 0; i < NumIntRegs; ++i)
69 dest->setIntReg(i, src->readIntReg(i));
70
71 // Then loop through the floating point registers.
72 for (int i = 0; i < NumFloatRegs; ++i)
73 dest->setFloatRegBits(i, src->readFloatRegBits(i));
74
75 // Would need to add condition-code regs if implemented
76 assert(NumCCRegs == 0);
77
78 // Copy misc. registers
79 copyMiscRegs(src, dest);
80
81 // Lastly copy PC/NPC
82 dest->pcState(src->pcState());
83}
84
85void
86copyMiscRegs(ThreadContext *src, ThreadContext *dest)
87{
88 dest->setMiscRegNoEffect(MISCREG_FPCR,
89 src->readMiscRegNoEffect(MISCREG_FPCR));
90 dest->setMiscRegNoEffect(MISCREG_UNIQ,
91 src->readMiscRegNoEffect(MISCREG_UNIQ));
92 dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
93 src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
94 dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
95 src->readMiscRegNoEffect(MISCREG_LOCKADDR));
96
97 copyIprs(src, dest);
98}
99
100void
101skipFunction(ThreadContext *tc)
102{
103 TheISA::PCState newPC = tc->pcState();
104 newPC.set(tc->readIntReg(ReturnAddressReg));
105 tc->pcState(newPC);
106}
107
108
109} // namespace AlphaISA
110
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