1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Ali Saidi
30 */
31
32#include "arch/alpha/utility.hh"
33#include "arch/alpha/vtophys.hh"
34#include "mem/vport.hh"
35#include "sim/full_system.hh"
36
37namespace AlphaISA {
38
39uint64_t
40getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
41{
42 if (FullSystem) {
43 const int NumArgumentRegs = 6;
44 if (number < NumArgumentRegs) {
45 if (fp)
46 return tc->readFloatRegBits(16 + number);
47 else
48 return tc->readIntReg(16 + number);
49 } else {
50 Addr sp = tc->readIntReg(StackPointerReg);
51 VirtualPort *vp = tc->getVirtPort();
52 uint64_t arg = vp->read<uint64_t>(sp +
53 (number-NumArgumentRegs) * sizeof(uint64_t));
54 return arg;
55 }
56 } else {
57 panic("getArgument() is Full system only\n");
58 M5_DUMMY_RETURN;
59 }
60}
61
62void
63copyRegs(ThreadContext *src, ThreadContext *dest)
64{
65 // First loop through the integer registers.
66 for (int i = 0; i < NumIntRegs; ++i)
67 dest->setIntReg(i, src->readIntReg(i));

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