1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 */
31
32#ifndef __ARCH_ALPHA_TYPES_HH__
33#define __ARCH_ALPHA_TYPES_HH__
34
35#include "base/types.hh"
36#include "arch/generic/types.hh"
37
38namespace AlphaISA {
39
40typedef uint32_t MachInst;
41typedef uint64_t ExtMachInst;
42
43typedef GenericISA::SimplePCState<MachInst> PCState;
44
45typedef uint64_t LargestRead;
46
47enum annotes
48{
49 ANNOTE_NONE = 0,
50 // An impossible number for instruction annotations
51 ITOUCH_ANNOTE = 0xffffffff,
52};
53
54struct CoreSpecific
55{
56 int core_type;
57};
58
59} // namespace AlphaISA
60
61#endif // __ARCH_ALPHA_TYPES_HH__