tlb.hh (5894:8091ac99341a) | tlb.hh (5999:3cf8e71257e0) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 107 unchanged lines hidden (view full) --- 116 EntryCache[0] = entry; 117 return entry; 118 } 119}; 120 121class ITB : public TLB 122{ 123 protected: | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 107 unchanged lines hidden (view full) --- 116 EntryCache[0] = entry; 117 return entry; 118 } 119}; 120 121class ITB : public TLB 122{ 123 protected: |
124 mutable Stats::Scalar<> hits; 125 mutable Stats::Scalar<> misses; 126 mutable Stats::Scalar<> acv; | 124 mutable Stats::Scalar hits; 125 mutable Stats::Scalar misses; 126 mutable Stats::Scalar acv; |
127 mutable Stats::Formula accesses; 128 129 public: 130 typedef AlphaITBParams Params; 131 ITB(const Params *p); 132 virtual void regStats(); 133 134 Fault translateAtomic(RequestPtr req, ThreadContext *tc); 135 void translateTiming(RequestPtr req, ThreadContext *tc, 136 Translation *translation); 137}; 138 139class DTB : public TLB 140{ 141 protected: | 127 mutable Stats::Formula accesses; 128 129 public: 130 typedef AlphaITBParams Params; 131 ITB(const Params *p); 132 virtual void regStats(); 133 134 Fault translateAtomic(RequestPtr req, ThreadContext *tc); 135 void translateTiming(RequestPtr req, ThreadContext *tc, 136 Translation *translation); 137}; 138 139class DTB : public TLB 140{ 141 protected: |
142 mutable Stats::Scalar<> read_hits; 143 mutable Stats::Scalar<> read_misses; 144 mutable Stats::Scalar<> read_acv; 145 mutable Stats::Scalar<> read_accesses; 146 mutable Stats::Scalar<> write_hits; 147 mutable Stats::Scalar<> write_misses; 148 mutable Stats::Scalar<> write_acv; 149 mutable Stats::Scalar<> write_accesses; | 142 mutable Stats::Scalar read_hits; 143 mutable Stats::Scalar read_misses; 144 mutable Stats::Scalar read_acv; 145 mutable Stats::Scalar read_accesses; 146 mutable Stats::Scalar write_hits; 147 mutable Stats::Scalar write_misses; 148 mutable Stats::Scalar write_acv; 149 mutable Stats::Scalar write_accesses; |
150 Stats::Formula hits; 151 Stats::Formula misses; 152 Stats::Formula acv; 153 Stats::Formula accesses; 154 155 public: 156 typedef AlphaDTBParams Params; 157 DTB(const Params *p); 158 virtual void regStats(); 159 160 Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write); 161 void translateTiming(RequestPtr req, ThreadContext *tc, 162 Translation *translation, bool write); 163}; 164 165} // namespace AlphaISA 166 167#endif // __ARCH_ALPHA_TLB_HH__ | 150 Stats::Formula hits; 151 Stats::Formula misses; 152 Stats::Formula acv; 153 Stats::Formula accesses; 154 155 public: 156 typedef AlphaDTBParams Params; 157 DTB(const Params *p); 158 virtual void regStats(); 159 160 Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write); 161 void translateTiming(RequestPtr req, ThreadContext *tc, 162 Translation *translation, bool write); 163}; 164 165} // namespace AlphaISA 166 167#endif // __ARCH_ALPHA_TLB_HH__ |