tlb.hh (5568:d14250d688d2) | tlb.hh (5569:baeee670d4ce) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 |
32#ifndef __ALPHA_MEMORY_HH__ 33#define __ALPHA_MEMORY_HH__ | 32#ifndef __ARCH_ALPHA_TLB_HH__ 33#define __ARCH_ALPHA_TLB_HH__ |
34 35#include <map> 36 37#include "arch/alpha/ev5.hh" 38#include "arch/alpha/isa_traits.hh" 39#include "arch/alpha/pagetable.hh" 40#include "arch/alpha/utility.hh" 41#include "arch/alpha/vtophys.hh" 42#include "base/statistics.hh" 43#include "mem/request.hh" 44#include "params/AlphaDTB.hh" 45#include "params/AlphaITB.hh" 46#include "sim/faults.hh" 47#include "sim/tlb.hh" 48 49class ThreadContext; 50 | 34 35#include <map> 36 37#include "arch/alpha/ev5.hh" 38#include "arch/alpha/isa_traits.hh" 39#include "arch/alpha/pagetable.hh" 40#include "arch/alpha/utility.hh" 41#include "arch/alpha/vtophys.hh" 42#include "base/statistics.hh" 43#include "mem/request.hh" 44#include "params/AlphaDTB.hh" 45#include "params/AlphaITB.hh" 46#include "sim/faults.hh" 47#include "sim/tlb.hh" 48 49class ThreadContext; 50 |
51namespace AlphaISA | 51namespace AlphaISA { 52 53class TlbEntry; 54 55class TLB : public BaseTLB |
52{ | 56{ |
53 class TlbEntry; | 57 protected: 58 typedef std::multimap<Addr, int> PageTable; 59 PageTable lookupTable; // Quick lookup into page table |
54 | 60 |
55 class TLB : public BaseTLB 56 { 57 protected: 58 typedef std::multimap<Addr, int> PageTable; 59 PageTable lookupTable; // Quick lookup into page table | 61 TlbEntry *table; // the Page Table 62 int size; // TLB Size 63 int nlu; // not last used entry (for replacement) |
60 | 64 |
61 TlbEntry *table; // the Page Table 62 int size; // TLB Size 63 int nlu; // not last used entry (for replacement) | 65 void nextnlu() { if (++nlu >= size) nlu = 0; } 66 TlbEntry *lookup(Addr vpn, uint8_t asn); |
64 | 67 |
65 void nextnlu() { if (++nlu >= size) nlu = 0; } 66 TlbEntry *lookup(Addr vpn, uint8_t asn); | 68 public: 69 typedef AlphaTLBParams Params; 70 TLB(const Params *p); 71 virtual ~TLB(); |
67 | 72 |
68 public: 69 typedef AlphaTLBParams Params; 70 TLB(const Params *p); 71 virtual ~TLB(); | 73 int getsize() const { return size; } |
72 | 74 |
73 int getsize() const { return size; } | 75 TlbEntry &index(bool advance = true); 76 void insert(Addr vaddr, TlbEntry &entry); |
74 | 77 |
75 TlbEntry &index(bool advance = true); 76 void insert(Addr vaddr, TlbEntry &entry); | 78 void flushAll(); 79 void flushProcesses(); 80 void flushAddr(Addr addr, uint8_t asn); |
77 | 81 |
78 void flushAll(); 79 void flushProcesses(); 80 void flushAddr(Addr addr, uint8_t asn); | 82 void 83 demapPage(Addr vaddr, uint64_t asn) 84 { 85 assert(asn < (1 << 8)); 86 flushAddr(vaddr, asn); 87 } |
81 | 88 |
82 void demapPage(Addr vaddr, uint64_t asn) 83 { 84 assert(asn < (1 << 8)); 85 flushAddr(vaddr, asn); 86 } | 89 // static helper functions... really EV5 VM traits 90 static bool 91 validVirtualAddress(Addr vaddr) 92 { 93 // unimplemented bits must be all 0 or all 1 94 Addr unimplBits = vaddr & VAddrUnImplMask; 95 return unimplBits == 0 || unimplBits == VAddrUnImplMask; 96 } |
87 | 97 |
88 // static helper functions... really EV5 VM traits 89 static bool validVirtualAddress(Addr vaddr) { 90 // unimplemented bits must be all 0 or all 1 91 Addr unimplBits = vaddr & VAddrUnImplMask; 92 return (unimplBits == 0) || (unimplBits == VAddrUnImplMask); 93 } | 98 static Fault checkCacheability(RequestPtr &req, bool itb = false); |
94 | 99 |
95 static Fault checkCacheability(RequestPtr &req, bool itb = false); | 100 // Checkpointing 101 virtual void serialize(std::ostream &os); 102 virtual void unserialize(Checkpoint *cp, const std::string §ion); |
96 | 103 |
97 // Checkpointing 98 virtual void serialize(std::ostream &os); 99 virtual void unserialize(Checkpoint *cp, const std::string §ion); | 104 // Most recently used page table entries 105 TlbEntry *EntryCache[3]; 106 inline void 107 flushCache() 108 { 109 memset(EntryCache, 0, 3 * sizeof(TlbEntry*)); 110 } |
100 | 111 |
101 // Most recently used page table entries 102 TlbEntry *EntryCache[3]; 103 inline void flushCache() 104 { 105 memset(EntryCache, 0, 3 * sizeof(TlbEntry*)); 106 } | 112 inline TlbEntry * 113 updateCache(TlbEntry *entry) { 114 EntryCache[2] = EntryCache[1]; 115 EntryCache[1] = EntryCache[0]; 116 EntryCache[0] = entry; 117 return entry; 118 } 119}; |
107 | 120 |
108 inline TlbEntry* updateCache(TlbEntry *entry) { 109 EntryCache[2] = EntryCache[1]; 110 EntryCache[1] = EntryCache[0]; 111 EntryCache[0] = entry; 112 return entry; 113 } 114 }; | 121class ITB : public TLB 122{ 123 protected: 124 mutable Stats::Scalar<> hits; 125 mutable Stats::Scalar<> misses; 126 mutable Stats::Scalar<> acv; 127 mutable Stats::Formula accesses; |
115 | 128 |
116 class ITB : public TLB 117 { 118 protected: 119 mutable Stats::Scalar<> hits; 120 mutable Stats::Scalar<> misses; 121 mutable Stats::Scalar<> acv; 122 mutable Stats::Formula accesses; | 129 public: 130 typedef AlphaITBParams Params; 131 ITB(const Params *p); 132 virtual void regStats(); |
123 | 133 |
124 public: 125 typedef AlphaITBParams Params; 126 ITB(const Params *p); 127 virtual void regStats(); | 134 Fault translate(RequestPtr &req, ThreadContext *tc); 135}; |
128 | 136 |
129 Fault translate(RequestPtr &req, ThreadContext *tc); 130 }; | 137class DTB : public TLB 138{ 139 protected: 140 mutable Stats::Scalar<> read_hits; 141 mutable Stats::Scalar<> read_misses; 142 mutable Stats::Scalar<> read_acv; 143 mutable Stats::Scalar<> read_accesses; 144 mutable Stats::Scalar<> write_hits; 145 mutable Stats::Scalar<> write_misses; 146 mutable Stats::Scalar<> write_acv; 147 mutable Stats::Scalar<> write_accesses; 148 Stats::Formula hits; 149 Stats::Formula misses; 150 Stats::Formula acv; 151 Stats::Formula accesses; |
131 | 152 |
132 class DTB : public TLB 133 { 134 protected: 135 mutable Stats::Scalar<> read_hits; 136 mutable Stats::Scalar<> read_misses; 137 mutable Stats::Scalar<> read_acv; 138 mutable Stats::Scalar<> read_accesses; 139 mutable Stats::Scalar<> write_hits; 140 mutable Stats::Scalar<> write_misses; 141 mutable Stats::Scalar<> write_acv; 142 mutable Stats::Scalar<> write_accesses; 143 Stats::Formula hits; 144 Stats::Formula misses; 145 Stats::Formula acv; 146 Stats::Formula accesses; | 153 public: 154 typedef AlphaDTBParams Params; 155 DTB(const Params *p); 156 virtual void regStats(); |
147 | 157 |
148 public: 149 typedef AlphaDTBParams Params; 150 DTB(const Params *p); 151 virtual void regStats(); | 158 Fault translate(RequestPtr &req, ThreadContext *tc, bool write); 159}; |
152 | 160 |
153 Fault translate(RequestPtr &req, ThreadContext *tc, bool write); 154 }; 155} | 161} // namespace AlphaISA |
156 | 162 |
157#endif // __ALPHA_MEMORY_HH__ | 163#endif // __ARCH_ALPHA_TLB_HH__ |