tlb.hh (5034:6186ef720dd4) tlb.hh (5358:e9acb84bbafb)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39#include "arch/alpha/pagetable.hh"
40#include "arch/alpha/utility.hh"
41#include "arch/alpha/vtophys.hh"
42#include "base/statistics.hh"
43#include "mem/request.hh"
44#include "params/AlphaDTB.hh"
45#include "params/AlphaITB.hh"
46#include "sim/faults.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39#include "arch/alpha/pagetable.hh"
40#include "arch/alpha/utility.hh"
41#include "arch/alpha/vtophys.hh"
42#include "base/statistics.hh"
43#include "mem/request.hh"
44#include "params/AlphaDTB.hh"
45#include "params/AlphaITB.hh"
46#include "sim/faults.hh"
47#include "sim/sim_object.hh"
47#include "sim/tlb.hh"
48
49class ThreadContext;
50
51namespace AlphaISA
52{
53 class TlbEntry;
54
48
49class ThreadContext;
50
51namespace AlphaISA
52{
53 class TlbEntry;
54
55 class TLB : public SimObject
55 class TLB : public BaseTLB
56 {
57 protected:
58 typedef std::multimap<Addr, int> PageTable;
59 PageTable lookupTable; // Quick lookup into page table
60
61 TlbEntry *table; // the Page Table
62 int size; // TLB Size
63 int nlu; // not last used entry (for replacement)

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74
75 TlbEntry &index(bool advance = true);
76 void insert(Addr vaddr, TlbEntry &entry);
77
78 void flushAll();
79 void flushProcesses();
80 void flushAddr(Addr addr, uint8_t asn);
81
56 {
57 protected:
58 typedef std::multimap<Addr, int> PageTable;
59 PageTable lookupTable; // Quick lookup into page table
60
61 TlbEntry *table; // the Page Table
62 int size; // TLB Size
63 int nlu; // not last used entry (for replacement)

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74
75 TlbEntry &index(bool advance = true);
76 void insert(Addr vaddr, TlbEntry &entry);
77
78 void flushAll();
79 void flushProcesses();
80 void flushAddr(Addr addr, uint8_t asn);
81
82 void demapPage(Addr vaddr, uint64_t asn)
83 {
84 assert(asn < (1 << 8));
85 flushAddr(vaddr, asn);
86 }
87
82 // static helper functions... really EV5 VM traits
83 static bool validVirtualAddress(Addr vaddr) {
84 // unimplemented bits must be all 0 or all 1
85 Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
86 return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
87 }
88
89 static Fault checkCacheability(RequestPtr &req);

--- 62 unchanged lines hidden --- 		88 // static helper functions... really EV5 VM traits
89 static bool validVirtualAddress(Addr vaddr) {
90 // unimplemented bits must be all 0 or all 1
91 Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
92 return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
93 }
94
95 static Fault checkCacheability(RequestPtr &req);

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