tlb.hh (4967:fb9a1d205359) tlb.hh (5004:7d94cedab264)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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43#include "mem/request.hh"
44#include "sim/faults.hh"
45#include "sim/sim_object.hh"
46
47class ThreadContext;
48
49namespace AlphaISA
50{
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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43#include "mem/request.hh"
44#include "sim/faults.hh"
45#include "sim/sim_object.hh"
46
47class ThreadContext;
48
49namespace AlphaISA
50{
51 class PTE;
51 class TlbEntry;
52
53 class TLB : public SimObject
54 {
55 protected:
56 typedef std::multimap<Addr, int> PageTable;
52
53 class TLB : public SimObject
54 {
55 protected:
56 typedef std::multimap<Addr, int> PageTable;
57 PageTable lookupTable; // Quick lookup into page table
57 PageTable lookupTable; // Quick lookup into page table
58
58
59 PTE *table; // the Page Table
60 int size; // TLB Size
61 int nlu; // not last used entry (for replacement)
59 TlbEntry *table; // the Page Table
60 int size; // TLB Size
61 int nlu; // not last used entry (for replacement)
62
63 void nextnlu() { if (++nlu >= size) nlu = 0; }
62
63 void nextnlu() { if (++nlu >= size) nlu = 0; }
64 PTE *lookup(Addr vpn, uint8_t asn);
64 TlbEntry *lookup(Addr vpn, uint8_t asn);
65
66 public:
67 TLB(const std::string &name, int size);
68 virtual ~TLB();
69
70 int getsize() const { return size; }
71
65
66 public:
67 TLB(const std::string &name, int size);
68 virtual ~TLB();
69
70 int getsize() const { return size; }
71
72 PTE &index(bool advance = true);
73 void insert(Addr vaddr, PTE &pte);
72 TlbEntry &index(bool advance = true);
73 void insert(Addr vaddr, TlbEntry &entry);
74
75 void flushAll();
76 void flushProcesses();
77 void flushAddr(Addr addr, uint8_t asn);
78
79 // static helper functions... really EV5 VM traits
80 static bool validVirtualAddress(Addr vaddr) {
81 // unimplemented bits must be all 0 or all 1
82 Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
83 return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
84 }
85
86 static Fault checkCacheability(RequestPtr &req);
87
88 // Checkpointing
89 virtual void serialize(std::ostream &os);
90 virtual void unserialize(Checkpoint *cp, const std::string &section);
91
92 // Most recently used page table entries
74
75 void flushAll();
76 void flushProcesses();
77 void flushAddr(Addr addr, uint8_t asn);
78
79 // static helper functions... really EV5 VM traits
80 static bool validVirtualAddress(Addr vaddr) {
81 // unimplemented bits must be all 0 or all 1
82 Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
83 return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
84 }
85
86 static Fault checkCacheability(RequestPtr &req);
87
88 // Checkpointing
89 virtual void serialize(std::ostream &os);
90 virtual void unserialize(Checkpoint *cp, const std::string &section);
91
92 // Most recently used page table entries
93 PTE *PTECache[3];
94 inline void flushCache() { memset(PTECache, 0, 3 * sizeof(PTE*)); }
95 inline PTE* updateCache(PTE *pte) {
96 PTECache[2] = PTECache[1];
97 PTECache[1] = PTECache[0];
98 PTECache[0] = pte;
99 return pte;
93 TlbEntry *EntryCache[3];
94 inline void flushCache()
95 {
96 memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
100 }
97 }
98
99 inline TlbEntry* updateCache(TlbEntry *entry) {
100 EntryCache[2] = EntryCache[1];
101 EntryCache[1] = EntryCache[0];
102 EntryCache[0] = entry;
103 return entry;
104 }
101 };
102
103 class ITB : public TLB
104 {
105 protected:
106 mutable Stats::Scalar<> hits;
107 mutable Stats::Scalar<> misses;
108 mutable Stats::Scalar<> acv;

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106
107 class ITB : public TLB
108 {
109 protected:
110 mutable Stats::Scalar<> hits;
111 mutable Stats::Scalar<> misses;
112 mutable Stats::Scalar<> acv;

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