tlb.hh (2984:797622d7b311) tlb.hh (3453:c3ce58882751)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31
32#ifndef __ALPHA_MEMORY_HH__
33#define __ALPHA_MEMORY_HH__
34
35#include <map>
36
37#include "arch/alpha/ev5.hh"
38#include "arch/alpha/isa_traits.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 22 unchanged lines hidden (view full) ---

31
32#ifndef __ALPHA_MEMORY_HH__
33#define __ALPHA_MEMORY_HH__
34
35#include <map>
36
37#include "arch/alpha/ev5.hh"
38#include "arch/alpha/isa_traits.hh"
39#include "arch/alpha/pagetable.hh"
39#include "arch/alpha/utility.hh"
40#include "arch/alpha/vtophys.hh"
41#include "base/statistics.hh"
42#include "mem/request.hh"
43#include "sim/faults.hh"
44#include "sim/sim_object.hh"
45
46class ThreadContext;
47
40#include "arch/alpha/utility.hh"
41#include "arch/alpha/vtophys.hh"
42#include "base/statistics.hh"
43#include "mem/request.hh"
44#include "sim/faults.hh"
45#include "sim/sim_object.hh"
46
47class ThreadContext;
48
48class AlphaTLB : public SimObject
49namespace AlphaISA
49{
50{
50 protected:
51 typedef std::multimap<Addr, int> PageTable;
52 PageTable lookupTable; // Quick lookup into page table
51 class PTE;
53
52
54 AlphaISA::PTE *table; // the Page Table
55 int size; // TLB Size
56 int nlu; // not last used entry (for replacement)
53 class TLB : public SimObject
54 {
55 protected:
56 typedef std::multimap<Addr, int> PageTable;
57 PageTable lookupTable; // Quick lookup into page table
57
58
58 void nextnlu() { if (++nlu >= size) nlu = 0; }
59 AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
59 PTE *table; // the Page Table
60 int size; // TLB Size
61 int nlu; // not last used entry (for replacement)
60
62
61 public:
62 AlphaTLB(const std::string &name, int size);
63 virtual ~AlphaTLB();
63 void nextnlu() { if (++nlu >= size) nlu = 0; }
64 PTE *lookup(Addr vpn, uint8_t asn) const;
64
65
65 int getsize() const { return size; }
66 public:
67 TLB(const std::string &name, int size);
68 virtual ~TLB();
66
69
67 AlphaISA::PTE &index(bool advance = true);
68 void insert(Addr vaddr, AlphaISA::PTE &pte);
70 int getsize() const { return size; }
69
71
70 void flushAll();
71 void flushProcesses();
72 void flushAddr(Addr addr, uint8_t asn);
72 PTE &index(bool advance = true);
73 void insert(Addr vaddr, PTE &pte);
73
74
74 // static helper functions... really EV5 VM traits
75 static bool validVirtualAddress(Addr vaddr) {
76 // unimplemented bits must be all 0 or all 1
77 Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
78 return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
79 }
75 void flushAll();
76 void flushProcesses();
77 void flushAddr(Addr addr, uint8_t asn);
80
78
81 static Fault checkCacheability(RequestPtr &req);
79 // static helper functions... really EV5 VM traits
80 static bool validVirtualAddress(Addr vaddr) {
81 // unimplemented bits must be all 0 or all 1
82 Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
83 return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
84 }
82
85
83 // Checkpointing
84 virtual void serialize(std::ostream &os);
85 virtual void unserialize(Checkpoint *cp, const std::string &section);
86};
86 static Fault checkCacheability(RequestPtr &req);
87
87
88class AlphaITB : public AlphaTLB
89{
90 protected:
91 mutable Stats::Scalar<> hits;
92 mutable Stats::Scalar<> misses;
93 mutable Stats::Scalar<> acv;
94 mutable Stats::Formula accesses;
88 // Checkpointing
89 virtual void serialize(std::ostream &os);
90 virtual void unserialize(Checkpoint *cp, const std::string &section);
91 };
95
92
96 public:
97 AlphaITB(const std::string &name, int size);
98 virtual void regStats();
93 class ITB : public TLB
94 {
95 protected:
96 mutable Stats::Scalar<> hits;
97 mutable Stats::Scalar<> misses;
98 mutable Stats::Scalar<> acv;
99 mutable Stats::Formula accesses;
99
100
100 Fault translate(RequestPtr &req, ThreadContext *tc) const;
101};
101 public:
102 ITB(const std::string &name, int size);
103 virtual void regStats();
102
104
103class AlphaDTB : public AlphaTLB
104{
105 protected:
106 mutable Stats::Scalar<> read_hits;
107 mutable Stats::Scalar<> read_misses;
108 mutable Stats::Scalar<> read_acv;
109 mutable Stats::Scalar<> read_accesses;
110 mutable Stats::Scalar<> write_hits;
111 mutable Stats::Scalar<> write_misses;
112 mutable Stats::Scalar<> write_acv;
113 mutable Stats::Scalar<> write_accesses;
114 Stats::Formula hits;
115 Stats::Formula misses;
116 Stats::Formula acv;
117 Stats::Formula accesses;
105 Fault translate(RequestPtr &req, ThreadContext *tc) const;
106 };
118
107
119 public:
120 AlphaDTB(const std::string &name, int size);
121 virtual void regStats();
108 class DTB : public TLB
109 {
110 protected:
111 mutable Stats::Scalar<> read_hits;
112 mutable Stats::Scalar<> read_misses;
113 mutable Stats::Scalar<> read_acv;
114 mutable Stats::Scalar<> read_accesses;
115 mutable Stats::Scalar<> write_hits;
116 mutable Stats::Scalar<> write_misses;
117 mutable Stats::Scalar<> write_acv;
118 mutable Stats::Scalar<> write_accesses;
119 Stats::Formula hits;
120 Stats::Formula misses;
121 Stats::Formula acv;
122 Stats::Formula accesses;
122
123
123 Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
124};
124 public:
125 DTB(const std::string &name, int size);
126 virtual void regStats();
125
127
128 Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
129 };
130}
131
126#endif // __ALPHA_MEMORY_HH__
132#endif // __ALPHA_MEMORY_HH__