32,33c32,33
< #ifndef __ALPHA_MEMORY_HH__
< #define __ALPHA_MEMORY_HH__
---
> #ifndef __ARCH_ALPHA_TLB_HH__
> #define __ARCH_ALPHA_TLB_HH__
51c51,55
< namespace AlphaISA
---
> namespace AlphaISA {
>
> class TlbEntry;
>
> class TLB : public BaseTLB
53c57,59
< class TlbEntry;
---
> protected:
> typedef std::multimap<Addr, int> PageTable;
> PageTable lookupTable; // Quick lookup into page table
55,59c61,63
< class TLB : public BaseTLB
< {
< protected:
< typedef std::multimap<Addr, int> PageTable;
< PageTable lookupTable; // Quick lookup into page table
---
> TlbEntry *table; // the Page Table
> int size; // TLB Size
> int nlu; // not last used entry (for replacement)
61,63c65,66
< TlbEntry *table; // the Page Table
< int size; // TLB Size
< int nlu; // not last used entry (for replacement)
---
> void nextnlu() { if (++nlu >= size) nlu = 0; }
> TlbEntry *lookup(Addr vpn, uint8_t asn);
65,66c68,71
< void nextnlu() { if (++nlu >= size) nlu = 0; }
< TlbEntry *lookup(Addr vpn, uint8_t asn);
---
> public:
> typedef AlphaTLBParams Params;
> TLB(const Params *p);
> virtual ~TLB();
68,71c73
< public:
< typedef AlphaTLBParams Params;
< TLB(const Params *p);
< virtual ~TLB();
---
> int getsize() const { return size; }
73c75,76
< int getsize() const { return size; }
---
> TlbEntry &index(bool advance = true);
> void insert(Addr vaddr, TlbEntry &entry);
75,76c78,80
< TlbEntry &index(bool advance = true);
< void insert(Addr vaddr, TlbEntry &entry);
---
> void flushAll();
> void flushProcesses();
> void flushAddr(Addr addr, uint8_t asn);
78,80c82,87
< void flushAll();
< void flushProcesses();
< void flushAddr(Addr addr, uint8_t asn);
---
> void
> demapPage(Addr vaddr, uint64_t asn)
> {
> assert(asn < (1 << 8));
> flushAddr(vaddr, asn);
> }
82,86c89,96
< void demapPage(Addr vaddr, uint64_t asn)
< {
< assert(asn < (1 << 8));
< flushAddr(vaddr, asn);
< }
---
> // static helper functions... really EV5 VM traits
> static bool
> validVirtualAddress(Addr vaddr)
> {
> // unimplemented bits must be all 0 or all 1
> Addr unimplBits = vaddr & VAddrUnImplMask;
> return unimplBits == 0 || unimplBits == VAddrUnImplMask;
> }
88,93c98
< // static helper functions... really EV5 VM traits
< static bool validVirtualAddress(Addr vaddr) {
< // unimplemented bits must be all 0 or all 1
< Addr unimplBits = vaddr & VAddrUnImplMask;
< return (unimplBits == 0) || (unimplBits == VAddrUnImplMask);
< }
---
> static Fault checkCacheability(RequestPtr &req, bool itb = false);
95c100,102
< static Fault checkCacheability(RequestPtr &req, bool itb = false);
---
> // Checkpointing
> virtual void serialize(std::ostream &os);
> virtual void unserialize(Checkpoint *cp, const std::string &section);
97,99c104,110
< // Checkpointing
< virtual void serialize(std::ostream &os);
< virtual void unserialize(Checkpoint *cp, const std::string &section);
---
> // Most recently used page table entries
> TlbEntry *EntryCache[3];
> inline void
> flushCache()
> {
> memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
> }
101,106c112,119
< // Most recently used page table entries
< TlbEntry *EntryCache[3];
< inline void flushCache()
< {
< memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
< }
---
> inline TlbEntry *
> updateCache(TlbEntry *entry) {
> EntryCache[2] = EntryCache[1];
> EntryCache[1] = EntryCache[0];
> EntryCache[0] = entry;
> return entry;
> }
> };
108,114c121,127
< inline TlbEntry* updateCache(TlbEntry *entry) {
< EntryCache[2] = EntryCache[1];
< EntryCache[1] = EntryCache[0];
< EntryCache[0] = entry;
< return entry;
< }
< };
---
> class ITB : public TLB
> {
> protected:
> mutable Stats::Scalar<> hits;
> mutable Stats::Scalar<> misses;
> mutable Stats::Scalar<> acv;
> mutable Stats::Formula accesses;
116,122c129,132
< class ITB : public TLB
< {
< protected:
< mutable Stats::Scalar<> hits;
< mutable Stats::Scalar<> misses;
< mutable Stats::Scalar<> acv;
< mutable Stats::Formula accesses;
---
> public:
> typedef AlphaITBParams Params;
> ITB(const Params *p);
> virtual void regStats();
124,127c134,135
< public:
< typedef AlphaITBParams Params;
< ITB(const Params *p);
< virtual void regStats();
---
> Fault translate(RequestPtr &req, ThreadContext *tc);
> };
129,130c137,151
< Fault translate(RequestPtr &req, ThreadContext *tc);
< };
---
> class DTB : public TLB
> {
> protected:
> mutable Stats::Scalar<> read_hits;
> mutable Stats::Scalar<> read_misses;
> mutable Stats::Scalar<> read_acv;
> mutable Stats::Scalar<> read_accesses;
> mutable Stats::Scalar<> write_hits;
> mutable Stats::Scalar<> write_misses;
> mutable Stats::Scalar<> write_acv;
> mutable Stats::Scalar<> write_accesses;
> Stats::Formula hits;
> Stats::Formula misses;
> Stats::Formula acv;
> Stats::Formula accesses;
132,146c153,156
< class DTB : public TLB
< {
< protected:
< mutable Stats::Scalar<> read_hits;
< mutable Stats::Scalar<> read_misses;
< mutable Stats::Scalar<> read_acv;
< mutable Stats::Scalar<> read_accesses;
< mutable Stats::Scalar<> write_hits;
< mutable Stats::Scalar<> write_misses;
< mutable Stats::Scalar<> write_acv;
< mutable Stats::Scalar<> write_accesses;
< Stats::Formula hits;
< Stats::Formula misses;
< Stats::Formula acv;
< Stats::Formula accesses;
---
> public:
> typedef AlphaDTBParams Params;
> DTB(const Params *p);
> virtual void regStats();
148,151c158,159
< public:
< typedef AlphaDTBParams Params;
< DTB(const Params *p);
< virtual void regStats();
---
> Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
> };
153,155c161
< Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
< };
< }
---
> } // namespace AlphaISA
157c163
< #endif // __ALPHA_MEMORY_HH__
---
> #endif // __ARCH_ALPHA_TLB_HH__