38a39
> #include "arch/alpha/pagetable.hh"
48c49
< class AlphaTLB : public SimObject
---
> namespace AlphaISA
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< protected:
< typedef std::multimap<Addr, int> PageTable;
< PageTable lookupTable; // Quick lookup into page table
---
> class PTE;
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< AlphaISA::PTE *table; // the Page Table
< int size; // TLB Size
< int nlu; // not last used entry (for replacement)
---
> class TLB : public SimObject
> {
> protected:
> typedef std::multimap<Addr, int> PageTable;
> PageTable lookupTable; // Quick lookup into page table
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< void nextnlu() { if (++nlu >= size) nlu = 0; }
< AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
---
> PTE *table; // the Page Table
> int size; // TLB Size
> int nlu; // not last used entry (for replacement)
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< public:
< AlphaTLB(const std::string &name, int size);
< virtual ~AlphaTLB();
---
> void nextnlu() { if (++nlu >= size) nlu = 0; }
> PTE *lookup(Addr vpn, uint8_t asn) const;
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< int getsize() const { return size; }
---
> public:
> TLB(const std::string &name, int size);
> virtual ~TLB();
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< AlphaISA::PTE &index(bool advance = true);
< void insert(Addr vaddr, AlphaISA::PTE &pte);
---
> int getsize() const { return size; }
70,72c72,73
< void flushAll();
< void flushProcesses();
< void flushAddr(Addr addr, uint8_t asn);
---
> PTE &index(bool advance = true);
> void insert(Addr vaddr, PTE &pte);
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< // static helper functions... really EV5 VM traits
< static bool validVirtualAddress(Addr vaddr) {
< // unimplemented bits must be all 0 or all 1
< Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
< return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
< }
---
> void flushAll();
> void flushProcesses();
> void flushAddr(Addr addr, uint8_t asn);
81c79,84
< static Fault checkCacheability(RequestPtr &req);
---
> // static helper functions... really EV5 VM traits
> static bool validVirtualAddress(Addr vaddr) {
> // unimplemented bits must be all 0 or all 1
> Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
> return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
> }
83,86c86
< // Checkpointing
< virtual void serialize(std::ostream &os);
< virtual void unserialize(Checkpoint *cp, const std::string &section);
< };
---
> static Fault checkCacheability(RequestPtr &req);
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< class AlphaITB : public AlphaTLB
< {
< protected:
< mutable Stats::Scalar<> hits;
< mutable Stats::Scalar<> misses;
< mutable Stats::Scalar<> acv;
< mutable Stats::Formula accesses;
---
> // Checkpointing
> virtual void serialize(std::ostream &os);
> virtual void unserialize(Checkpoint *cp, const std::string &section);
> };
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< public:
< AlphaITB(const std::string &name, int size);
< virtual void regStats();
---
> class ITB : public TLB
> {
> protected:
> mutable Stats::Scalar<> hits;
> mutable Stats::Scalar<> misses;
> mutable Stats::Scalar<> acv;
> mutable Stats::Formula accesses;
100,101c101,103
< Fault translate(RequestPtr &req, ThreadContext *tc) const;
< };
---
> public:
> ITB(const std::string &name, int size);
> virtual void regStats();
103,117c105,106
< class AlphaDTB : public AlphaTLB
< {
< protected:
< mutable Stats::Scalar<> read_hits;
< mutable Stats::Scalar<> read_misses;
< mutable Stats::Scalar<> read_acv;
< mutable Stats::Scalar<> read_accesses;
< mutable Stats::Scalar<> write_hits;
< mutable Stats::Scalar<> write_misses;
< mutable Stats::Scalar<> write_acv;
< mutable Stats::Scalar<> write_accesses;
< Stats::Formula hits;
< Stats::Formula misses;
< Stats::Formula acv;
< Stats::Formula accesses;
---
> Fault translate(RequestPtr &req, ThreadContext *tc) const;
> };
119,121c108,122
< public:
< AlphaDTB(const std::string &name, int size);
< virtual void regStats();
---
> class DTB : public TLB
> {
> protected:
> mutable Stats::Scalar<> read_hits;
> mutable Stats::Scalar<> read_misses;
> mutable Stats::Scalar<> read_acv;
> mutable Stats::Scalar<> read_accesses;
> mutable Stats::Scalar<> write_hits;
> mutable Stats::Scalar<> write_misses;
> mutable Stats::Scalar<> write_acv;
> mutable Stats::Scalar<> write_accesses;
> Stats::Formula hits;
> Stats::Formula misses;
> Stats::Formula acv;
> Stats::Formula accesses;
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< Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
< };
---
> public:
> DTB(const std::string &name, int size);
> virtual void regStats();
125a128,131
> Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
> };
> }
>