tlb.cc (8737:770ccf3af571) | tlb.cc (8738:66bf413b0d5b) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37#include "arch/alpha/pagetable.hh" 38#include "arch/alpha/tlb.hh" 39#include "arch/generic/debugfaults.hh" 40#include "base/inifile.hh" 41#include "base/str.hh" 42#include "base/trace.hh" 43#include "cpu/thread_context.hh" 44#include "debug/TLB.hh" | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37#include "arch/alpha/pagetable.hh" 38#include "arch/alpha/tlb.hh" 39#include "arch/generic/debugfaults.hh" 40#include "base/inifile.hh" 41#include "base/str.hh" 42#include "base/trace.hh" 43#include "cpu/thread_context.hh" 44#include "debug/TLB.hh" |
45#include "sim/full_system.hh" |
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45 46using namespace std; 47 48namespace AlphaISA { 49 50/////////////////////////////////////////////////////////////////////// 51// 52// Alpha TLB --- 5 unchanged lines hidden (view full) --- 58#endif 59 60#define MODE2MASK(X) (1 << (X)) 61 62TLB::TLB(const Params *p) 63 : BaseTLB(p), size(p->size), nlu(0) 64{ 65 table = new TlbEntry[size]; | 46 47using namespace std; 48 49namespace AlphaISA { 50 51/////////////////////////////////////////////////////////////////////// 52// 53// Alpha TLB --- 5 unchanged lines hidden (view full) --- 59#endif 60 61#define MODE2MASK(X) (1 << (X)) 62 63TLB::TLB(const Params *p) 64 : BaseTLB(p), size(p->size), nlu(0) 65{ 66 table = new TlbEntry[size]; |
66 memset(table, 0, sizeof(TlbEntry) * size); | 67 memset(table, 0, sizeof(TlbEntry[size])); |
67 flushCache(); 68} 69 70TLB::~TLB() 71{ 72 if (table) 73 delete [] table; 74} --- 199 unchanged lines hidden (view full) --- 274 lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 275 nextnlu(); 276} 277 278void 279TLB::flushAll() 280{ 281 DPRINTF(TLB, "flushAll\n"); | 68 flushCache(); 69} 70 71TLB::~TLB() 72{ 73 if (table) 74 delete [] table; 75} --- 199 unchanged lines hidden (view full) --- 275 lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 276 nextnlu(); 277} 278 279void 280TLB::flushAll() 281{ 282 DPRINTF(TLB, "flushAll\n"); |
282 memset(table, 0, sizeof(TlbEntry) * size); | 283 memset(table, 0, sizeof(TlbEntry[size])); |
283 flushCache(); 284 lookupTable.clear(); 285 nlu = 0; 286} 287 288void 289TLB::flushProcesses() 290{ --- 74 unchanged lines hidden (view full) --- 365 } 366 } 367} 368 369Fault 370TLB::translateInst(RequestPtr req, ThreadContext *tc) 371{ 372 //If this is a pal pc, then set PHYSICAL | 284 flushCache(); 285 lookupTable.clear(); 286 nlu = 0; 287} 288 289void 290TLB::flushProcesses() 291{ --- 74 unchanged lines hidden (view full) --- 366 } 367 } 368} 369 370Fault 371TLB::translateInst(RequestPtr req, ThreadContext *tc) 372{ 373 //If this is a pal pc, then set PHYSICAL |
373 if (FULL_SYSTEM && PcPAL(req->getPC())) | 374 if (FullSystem && PcPAL(req->getPC())) |
374 req->setFlags(Request::PHYSICAL); 375 376 if (PcPAL(req->getPC())) { 377 // strip off PAL PC marker (lsb is 1) 378 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 379 fetch_hits++; 380 return NoFault; 381 } --- 227 unchanged lines hidden --- | 375 req->setFlags(Request::PHYSICAL); 376 377 if (PcPAL(req->getPC())) { 378 // strip off PAL PC marker (lsb is 1) 379 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 380 fetch_hits++; 381 return NoFault; 382 } --- 227 unchanged lines hidden --- |