tlb.cc (5894:8091ac99341a) tlb.cc (6022:410194bb3049)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 58 unchanged lines hidden (view full) ---

67}
68
69TLB::~TLB()
70{
71 if (table)
72 delete [] table;
73}
74
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 58 unchanged lines hidden (view full) ---

67}
68
69TLB::~TLB()
70{
71 if (table)
72 delete [] table;
73}
74
75void
76TLB::regStats()
77{
78 fetch_hits
79 .name(name() + ".fetch_hits")
80 .desc("ITB hits");
81 fetch_misses
82 .name(name() + ".fetch_misses")
83 .desc("ITB misses");
84 fetch_acv
85 .name(name() + ".fetch_acv")
86 .desc("ITB acv");
87 fetch_accesses
88 .name(name() + ".fetch_accesses")
89 .desc("ITB accesses");
90
91 fetch_accesses = fetch_hits + fetch_misses;
92
93 read_hits
94 .name(name() + ".read_hits")
95 .desc("DTB read hits")
96 ;
97
98 read_misses
99 .name(name() + ".read_misses")
100 .desc("DTB read misses")
101 ;
102
103 read_acv
104 .name(name() + ".read_acv")
105 .desc("DTB read access violations")
106 ;
107
108 read_accesses
109 .name(name() + ".read_accesses")
110 .desc("DTB read accesses")
111 ;
112
113 write_hits
114 .name(name() + ".write_hits")
115 .desc("DTB write hits")
116 ;
117
118 write_misses
119 .name(name() + ".write_misses")
120 .desc("DTB write misses")
121 ;
122
123 write_acv
124 .name(name() + ".write_acv")
125 .desc("DTB write access violations")
126 ;
127
128 write_accesses
129 .name(name() + ".write_accesses")
130 .desc("DTB write accesses")
131 ;
132
133 data_hits
134 .name(name() + ".data_hits")
135 .desc("DTB hits")
136 ;
137
138 data_misses
139 .name(name() + ".data_misses")
140 .desc("DTB misses")
141 ;
142
143 data_acv
144 .name(name() + ".data_acv")
145 .desc("DTB access violations")
146 ;
147
148 data_accesses
149 .name(name() + ".data_accesses")
150 .desc("DTB accesses")
151 ;
152
153 data_hits = read_hits + write_hits;
154 data_misses = read_misses + write_misses;
155 data_acv = read_acv + write_acv;
156 data_accesses = read_accesses + write_accesses;
157}
158
75// look up an entry in the TLB
76TlbEntry *
77TLB::lookup(Addr vpn, uint8_t asn)
78{
79 // assume not found...
80 TlbEntry *retval = NULL;
81
82 if (EntryCache[0]) {

--- 200 unchanged lines hidden (view full) ---

283 for (int i = 0; i < size; i++) {
284 table[i].unserialize(cp, csprintf("%s.Entry%d", section, i));
285 if (table[i].valid) {
286 lookupTable.insert(make_pair(table[i].tag, i));
287 }
288 }
289}
290
159// look up an entry in the TLB
160TlbEntry *
161TLB::lookup(Addr vpn, uint8_t asn)
162{
163 // assume not found...
164 TlbEntry *retval = NULL;
165
166 if (EntryCache[0]) {

--- 200 unchanged lines hidden (view full) ---

367 for (int i = 0; i < size; i++) {
368 table[i].unserialize(cp, csprintf("%s.Entry%d", section, i));
369 if (table[i].valid) {
370 lookupTable.insert(make_pair(table[i].tag, i));
371 }
372 }
373}
374
291///////////////////////////////////////////////////////////////////////
292//
293// Alpha ITB
294//
295ITB::ITB(const Params *p)
296 : TLB(p)
297{}
298
299
300void
301ITB::regStats()
302{
303 hits
304 .name(name() + ".hits")
305 .desc("ITB hits");
306 misses
307 .name(name() + ".misses")
308 .desc("ITB misses");
309 acv
310 .name(name() + ".acv")
311 .desc("ITB acv");
312 accesses
313 .name(name() + ".accesses")
314 .desc("ITB accesses");
315
316 accesses = hits + misses;
317}
318
319Fault
375Fault
320ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
376TLB::translateInst(RequestPtr req, ThreadContext *tc)
321{
322 //If this is a pal pc, then set PHYSICAL
323 if (FULL_SYSTEM && PcPAL(req->getPC()))
324 req->setFlags(Request::PHYSICAL);
325
326 if (PcPAL(req->getPC())) {
327 // strip off PAL PC marker (lsb is 1)
328 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
377{
378 //If this is a pal pc, then set PHYSICAL
379 if (FULL_SYSTEM && PcPAL(req->getPC()))
380 req->setFlags(Request::PHYSICAL);
381
382 if (PcPAL(req->getPC())) {
383 // strip off PAL PC marker (lsb is 1)
384 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
329 hits++;
385 fetch_hits++;
330 return NoFault;
331 }
332
333 if (req->getFlags() & Request::PHYSICAL) {
334 req->setPaddr(req->getVaddr());
335 } else {
336 // verify that this is a good virtual address
337 if (!validVirtualAddress(req->getVaddr())) {
386 return NoFault;
387 }
388
389 if (req->getFlags() & Request::PHYSICAL) {
390 req->setPaddr(req->getVaddr());
391 } else {
392 // verify that this is a good virtual address
393 if (!validVirtualAddress(req->getVaddr())) {
338 acv++;
394 fetch_acv++;
339 return new ItbAcvFault(req->getVaddr());
340 }
341
342
343 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
344 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
345#if ALPHA_TLASER
346 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
347 VAddrSpaceEV5(req->getVaddr()) == 2)
348#else
349 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
350#endif
351 {
352 // only valid in kernel mode
353 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
354 mode_kernel) {
395 return new ItbAcvFault(req->getVaddr());
396 }
397
398
399 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
400 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
401#if ALPHA_TLASER
402 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
403 VAddrSpaceEV5(req->getVaddr()) == 2)
404#else
405 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
406#endif
407 {
408 // only valid in kernel mode
409 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
410 mode_kernel) {
355 acv++;
411 fetch_acv++;
356 return new ItbAcvFault(req->getVaddr());
357 }
358
359 req->setPaddr(req->getVaddr() & PAddrImplMask);
360
361#if !ALPHA_TLASER
362 // sign extend the physical address properly
363 if (req->getPaddr() & PAddrUncachedBit40)

--- 4 unchanged lines hidden (view full) ---

368
369 } else {
370 // not a physical address: need to look up pte
371 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
372 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(),
373 asn);
374
375 if (!entry) {
412 return new ItbAcvFault(req->getVaddr());
413 }
414
415 req->setPaddr(req->getVaddr() & PAddrImplMask);
416
417#if !ALPHA_TLASER
418 // sign extend the physical address properly
419 if (req->getPaddr() & PAddrUncachedBit40)

--- 4 unchanged lines hidden (view full) ---

424
425 } else {
426 // not a physical address: need to look up pte
427 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
428 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(),
429 asn);
430
431 if (!entry) {
376 misses++;
432 fetch_misses++;
377 return new ItbPageFault(req->getVaddr());
378 }
379
380 req->setPaddr((entry->ppn << PageShift) +
381 (VAddr(req->getVaddr()).offset()
382 & ~3));
383
384 // check permissions for this access
385 if (!(entry->xre &
386 (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
387 // instruction access fault
433 return new ItbPageFault(req->getVaddr());
434 }
435
436 req->setPaddr((entry->ppn << PageShift) +
437 (VAddr(req->getVaddr()).offset()
438 & ~3));
439
440 // check permissions for this access
441 if (!(entry->xre &
442 (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
443 // instruction access fault
388 acv++;
444 fetch_acv++;
389 return new ItbAcvFault(req->getVaddr());
390 }
391
445 return new ItbAcvFault(req->getVaddr());
446 }
447
392 hits++;
448 fetch_hits++;
393 }
394 }
395
396 // check that the physical address is ok (catch bad physical addresses)
397 if (req->getPaddr() & ~PAddrImplMask)
398 return genMachineCheckFault();
399
400 return checkCacheability(req, true);
401
402}
403
449 }
450 }
451
452 // check that the physical address is ok (catch bad physical addresses)
453 if (req->getPaddr() & ~PAddrImplMask)
454 return genMachineCheckFault();
455
456 return checkCacheability(req, true);
457
458}
459
404void
405ITB::translateTiming(RequestPtr req, ThreadContext *tc,
406 Translation *translation)
407{
408 assert(translation);
409 translation->finish(translateAtomic(req, tc), req, tc, false);
410}
411
412///////////////////////////////////////////////////////////////////////
413//
414// Alpha DTB
415//
416DTB::DTB(const Params *p)
417 : TLB(p)
418{}
419
420void
421DTB::regStats()
422{
423 read_hits
424 .name(name() + ".read_hits")
425 .desc("DTB read hits")
426 ;
427
428 read_misses
429 .name(name() + ".read_misses")
430 .desc("DTB read misses")
431 ;
432
433 read_acv
434 .name(name() + ".read_acv")
435 .desc("DTB read access violations")
436 ;
437
438 read_accesses
439 .name(name() + ".read_accesses")
440 .desc("DTB read accesses")
441 ;
442
443 write_hits
444 .name(name() + ".write_hits")
445 .desc("DTB write hits")
446 ;
447
448 write_misses
449 .name(name() + ".write_misses")
450 .desc("DTB write misses")
451 ;
452
453 write_acv
454 .name(name() + ".write_acv")
455 .desc("DTB write access violations")
456 ;
457
458 write_accesses
459 .name(name() + ".write_accesses")
460 .desc("DTB write accesses")
461 ;
462
463 hits
464 .name(name() + ".hits")
465 .desc("DTB hits")
466 ;
467
468 misses
469 .name(name() + ".misses")
470 .desc("DTB misses")
471 ;
472
473 acv
474 .name(name() + ".acv")
475 .desc("DTB access violations")
476 ;
477
478 accesses
479 .name(name() + ".accesses")
480 .desc("DTB accesses")
481 ;
482
483 hits = read_hits + write_hits;
484 misses = read_misses + write_misses;
485 acv = read_acv + write_acv;
486 accesses = read_accesses + write_accesses;
487}
488
489Fault
460Fault
490DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
461TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
491{
492 Addr pc = tc->readPC();
493
494 mode_type mode =
495 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
496
497 /**
498 * Check for alignment faults

--- 120 unchanged lines hidden (view full) ---

619
620 // check that the physical address is ok (catch bad physical addresses)
621 if (req->getPaddr() & ~PAddrImplMask)
622 return genMachineCheckFault();
623
624 return checkCacheability(req);
625}
626
462{
463 Addr pc = tc->readPC();
464
465 mode_type mode =
466 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
467
468 /**
469 * Check for alignment faults

--- 120 unchanged lines hidden (view full) ---

590
591 // check that the physical address is ok (catch bad physical addresses)
592 if (req->getPaddr() & ~PAddrImplMask)
593 return genMachineCheckFault();
594
595 return checkCacheability(req);
596}
597
627void
628DTB::translateTiming(RequestPtr req, ThreadContext *tc,
629 Translation *translation, bool write)
630{
631 assert(translation);
632 translation->finish(translateAtomic(req, tc, write), req, tc, write);
633}
634
635TlbEntry &
636TLB::index(bool advance)
637{
638 TlbEntry *entry = &table[nlu];
639
640 if (advance)
641 nextnlu();
642
643 return *entry;
644}
645
598TlbEntry &
599TLB::index(bool advance)
600{
601 TlbEntry *entry = &table[nlu];
602
603 if (advance)
604 nextnlu();
605
606 return *entry;
607}
608
646/* end namespace AlphaISA */ }
609Fault
610TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
611 bool write, bool execute)
612{
613 if (execute)
614 return translateInst(req, tc);
615 else
616 return translateData(req, tc, write);
617}
647
618
648AlphaISA::ITB *
649AlphaITBParams::create()
619void
620TLB::translateTiming(RequestPtr req, ThreadContext *tc,
621 Translation *translation,
622 bool write, bool execute)
650{
623{
651 return new AlphaISA::ITB(this);
624 assert(translation);
625 translation->finish(translateAtomic(req, tc, write, execute),
626 req, tc, write, execute);
652}
653
627}
628
654AlphaISA::DTB *
655AlphaDTBParams::create()
629/* end namespace AlphaISA */ }
630
631AlphaISA::TLB *
632AlphaTLBParams::create()
656{
633{
657 return new AlphaISA::DTB(this);
634 return new AlphaISA::TLB(this);
658}
635}