tlb.cc (5891:73084c6bb183) tlb.cc (5894:8091ac99341a)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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312 accesses
313 .name(name() + ".accesses")
314 .desc("ITB accesses");
315
316 accesses = hits + misses;
317}
318
319Fault
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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312 accesses
313 .name(name() + ".accesses")
314 .desc("ITB accesses");
315
316 accesses = hits + misses;
317}
318
319Fault
320ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
320ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
321{
322 //If this is a pal pc, then set PHYSICAL
323 if (FULL_SYSTEM && PcPAL(req->getPC()))
324 req->setFlags(Request::PHYSICAL);
325
326 if (PcPAL(req->getPC())) {
327 // strip off PAL PC marker (lsb is 1)
328 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);

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396 // check that the physical address is ok (catch bad physical addresses)
397 if (req->getPaddr() & ~PAddrImplMask)
398 return genMachineCheckFault();
399
400 return checkCacheability(req, true);
401
402}
403
321{
322 //If this is a pal pc, then set PHYSICAL
323 if (FULL_SYSTEM && PcPAL(req->getPC()))
324 req->setFlags(Request::PHYSICAL);
325
326 if (PcPAL(req->getPC())) {
327 // strip off PAL PC marker (lsb is 1)
328 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);

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396 // check that the physical address is ok (catch bad physical addresses)
397 if (req->getPaddr() & ~PAddrImplMask)
398 return genMachineCheckFault();
399
400 return checkCacheability(req, true);
401
402}
403
404void
405ITB::translateTiming(RequestPtr req, ThreadContext *tc,
406 Translation *translation)
407{
408 assert(translation);
409 translation->finish(translateAtomic(req, tc), req, tc, false);
410}
411
404///////////////////////////////////////////////////////////////////////
405//
406// Alpha DTB
407//
408DTB::DTB(const Params *p)
409 : TLB(p)
410{}
411

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474
475 hits = read_hits + write_hits;
476 misses = read_misses + write_misses;
477 acv = read_acv + write_acv;
478 accesses = read_accesses + write_accesses;
479}
480
481Fault
412///////////////////////////////////////////////////////////////////////
413//
414// Alpha DTB
415//
416DTB::DTB(const Params *p)
417 : TLB(p)
418{}
419

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482
483 hits = read_hits + write_hits;
484 misses = read_misses + write_misses;
485 acv = read_acv + write_acv;
486 accesses = read_accesses + write_accesses;
487}
488
489Fault
482DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
490DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
483{
484 Addr pc = tc->readPC();
485
486 mode_type mode =
487 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
488
489 /**
490 * Check for alignment faults

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611
612 // check that the physical address is ok (catch bad physical addresses)
613 if (req->getPaddr() & ~PAddrImplMask)
614 return genMachineCheckFault();
615
616 return checkCacheability(req);
617}
618
491{
492 Addr pc = tc->readPC();
493
494 mode_type mode =
495 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
496
497 /**
498 * Check for alignment faults

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619
620 // check that the physical address is ok (catch bad physical addresses)
621 if (req->getPaddr() & ~PAddrImplMask)
622 return genMachineCheckFault();
623
624 return checkCacheability(req);
625}
626
627void
628DTB::translateTiming(RequestPtr req, ThreadContext *tc,
629 Translation *translation, bool write)
630{
631 assert(translation);
632 translation->finish(translateAtomic(req, tc, write), req, tc, write);
633}
634
619TlbEntry &
620TLB::index(bool advance)
621{
622 TlbEntry *entry = &table[nlu];
623
624 if (advance)
625 nextnlu();
626

--- 16 unchanged lines hidden --- 		635TlbEntry &
636TLB::index(bool advance)
637{
638 TlbEntry *entry = &table[nlu];
639
640 if (advance)
641 nextnlu();
642

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