tlb.cc (5569:baeee670d4ce) tlb.cc (5736:426510e758ad)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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137 if (req->getPaddr() & PAddrUncachedBit43)
138#endif
139 {
140 // IPR memory space not implemented
141 if (PAddrIprSpace(req->getPaddr())) {
142 return new UnimpFault("IPR memory space not implemented!");
143 } else {
144 // mark request as uncacheable
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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137 if (req->getPaddr() & PAddrUncachedBit43)
138#endif
139 {
140 // IPR memory space not implemented
141 if (PAddrIprSpace(req->getPaddr())) {
142 return new UnimpFault("IPR memory space not implemented!");
143 } else {
144 // mark request as uncacheable
145 req->setFlags(req->getFlags() | UNCACHEABLE);
145 req->setFlags(Request::UNCACHEABLE);
146
147#if !ALPHA_TLASER
148 // Clear bits 42:35 of the physical address (10-2 in
149 // Tsunami manual)
150 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
151#endif
152 }
153 // We shouldn't be able to read from an uncachable address in Alpha as

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316 accesses = hits + misses;
317}
318
319Fault
320ITB::translate(RequestPtr &req, ThreadContext *tc)
321{
322 //If this is a pal pc, then set PHYSICAL
323 if (FULL_SYSTEM && PcPAL(req->getPC()))
146
147#if !ALPHA_TLASER
148 // Clear bits 42:35 of the physical address (10-2 in
149 // Tsunami manual)
150 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
151#endif
152 }
153 // We shouldn't be able to read from an uncachable address in Alpha as

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316 accesses = hits + misses;
317}
318
319Fault
320ITB::translate(RequestPtr &req, ThreadContext *tc)
321{
322 //If this is a pal pc, then set PHYSICAL
323 if (FULL_SYSTEM && PcPAL(req->getPC()))
324 req->setFlags(req->getFlags() | PHYSICAL);
324 req->setFlags(Request::PHYSICAL);
325
326 if (PcPAL(req->getPC())) {
327 // strip off PAL PC marker (lsb is 1)
328 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
329 hits++;
330 return NoFault;
331 }
332
325
326 if (PcPAL(req->getPC())) {
327 // strip off PAL PC marker (lsb is 1)
328 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
329 hits++;
330 return NoFault;
331 }
332
333 if (req->getFlags() & PHYSICAL) {
333 if (req->getFlags() & Request::PHYSICAL) {
334 req->setPaddr(req->getVaddr());
335 } else {
336 // verify that this is a good virtual address
337 if (!validVirtualAddress(req->getVaddr())) {
338 acv++;
339 return new ItbAcvFault(req->getVaddr());
340 }
341

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492 if (req->getVaddr() & (req->getSize() - 1)) {
493 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
494 req->getSize());
495 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
496 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
497 }
498
499 if (PcPAL(pc)) {
334 req->setPaddr(req->getVaddr());
335 } else {
336 // verify that this is a good virtual address
337 if (!validVirtualAddress(req->getVaddr())) {
338 acv++;
339 return new ItbAcvFault(req->getVaddr());
340 }
341

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492 if (req->getVaddr() & (req->getSize() - 1)) {
493 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
494 req->getSize());
495 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
496 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
497 }
498
499 if (PcPAL(pc)) {
500 mode = (req->getFlags() & ALTMODE) ?
500 mode = (req->getFlags() & Request::ALTMODE) ?
501 (mode_type)ALT_MODE_AM(
502 tc->readMiscRegNoEffect(IPR_ALT_MODE))
503 : mode_kernel;
504 }
505
501 (mode_type)ALT_MODE_AM(
502 tc->readMiscRegNoEffect(IPR_ALT_MODE))
503 : mode_kernel;
504 }
505
506 if (req->getFlags() & PHYSICAL) {
506 if (req->getFlags() & Request::PHYSICAL) {
507 req->setPaddr(req->getVaddr());
508 } else {
509 // verify that this is a good virtual address
510 if (!validVirtualAddress(req->getVaddr())) {
511 if (write) { write_acv++; } else { read_acv++; }
512 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
513 MM_STAT_BAD_VA_MASK |
514 MM_STAT_ACV_MASK;

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555 // not a physical address: need to look up pte
556 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn);
557
558 if (!entry) {
559 // page fault
560 if (write) { write_misses++; } else { read_misses++; }
561 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
562 MM_STAT_DTB_MISS_MASK;
507 req->setPaddr(req->getVaddr());
508 } else {
509 // verify that this is a good virtual address
510 if (!validVirtualAddress(req->getVaddr())) {
511 if (write) { write_acv++; } else { read_acv++; }
512 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
513 MM_STAT_BAD_VA_MASK |
514 MM_STAT_ACV_MASK;

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555 // not a physical address: need to look up pte
556 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn);
557
558 if (!entry) {
559 // page fault
560 if (write) { write_misses++; } else { read_misses++; }
561 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
562 MM_STAT_DTB_MISS_MASK;
563 return (req->getFlags() & VPTE) ?
563 return (req->getFlags() & Request::VPTE) ?
564 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
565 flags)) :
566 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
567 flags));
568 }
569
570 req->setPaddr((entry->ppn << PageShift) +
571 VAddr(req->getVaddr()).offset());

--- 71 unchanged lines hidden --- 		564 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
565 flags)) :
566 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
567 flags));
568 }
569
570 req->setPaddr((entry->ppn << PageShift) +
571 VAddr(req->getVaddr()).offset());

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