tlb.cc (5358:e9acb84bbafb) tlb.cc (5532:d8ab33f5ff9a)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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111
112 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
113 retval ? "hit" : "miss", retval ? retval->ppn : 0);
114 return retval;
115}
116
117
118Fault
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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111
112 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
113 retval ? "hit" : "miss", retval ? retval->ppn : 0);
114 return retval;
115}
116
117
118Fault
119TLB::checkCacheability(RequestPtr &req)
119TLB::checkCacheability(RequestPtr &req, bool itb)
120{
121// in Alpha, cacheability is controlled by upper-level bits of the
122// physical address
123
124/*
125 * We support having the uncacheable bit in either bit 39 or bit 40.
126 * The Turbolaser platform (and EV5) support having the bit in 39, but
127 * Tsunami (which Linux assumes uses an EV6) generates accesses with

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143 // mark request as uncacheable
144 req->setFlags(req->getFlags() | UNCACHEABLE);
145
146#if !ALPHA_TLASER
147 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
148 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
149#endif
150 }
120{
121// in Alpha, cacheability is controlled by upper-level bits of the
122// physical address
123
124/*
125 * We support having the uncacheable bit in either bit 39 or bit 40.
126 * The Turbolaser platform (and EV5) support having the bit in 39, but
127 * Tsunami (which Linux assumes uses an EV6) generates accesses with

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143 // mark request as uncacheable
144 req->setFlags(req->getFlags() | UNCACHEABLE);
145
146#if !ALPHA_TLASER
147 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
148 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
149#endif
150 }
151 // We shouldn't be able to read from an uncachable address in Alpha as
152 // we don't have a ROM and we don't want to try to fetch from a device
153 // register as we destroy any data that is clear-on-read.
154 if (req->isUncacheable() && itb)
155 return new UnimpFault("CPU trying to fetch from uncached I/O");
156
151 }
152 return NoFault;
153}
154
155
156// insert a new TLB entry
157void
158TLB::insert(Addr addr, TlbEntry &entry)

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385 hits++;
386 }
387 }
388
389 // check that the physical address is ok (catch bad physical addresses)
390 if (req->getPaddr() & ~PAddrImplMask)
391 return genMachineCheckFault();
392
157 }
158 return NoFault;
159}
160
161
162// insert a new TLB entry
163void
164TLB::insert(Addr addr, TlbEntry &entry)

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391 hits++;
392 }
393 }
394
395 // check that the physical address is ok (catch bad physical addresses)
396 if (req->getPaddr() & ~PAddrImplMask)
397 return genMachineCheckFault();
398
393 return checkCacheability(req);
399 return checkCacheability(req, true);
394
395}
396
397///////////////////////////////////////////////////////////////////////
398//
399// Alpha DTB
400//
401 DTB::DTB(const Params *p)

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401}
402
403///////////////////////////////////////////////////////////////////////
404//
405// Alpha DTB
406//
407 DTB::DTB(const Params *p)

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