tlb.cc (5004:7d94cedab264) | tlb.cc (5034:6186ef720dd4) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36#include "arch/alpha/pagetable.hh" 37#include "arch/alpha/tlb.hh" 38#include "arch/alpha/faults.hh" 39#include "base/inifile.hh" 40#include "base/str.hh" 41#include "base/trace.hh" 42#include "config/alpha_tlaser.hh" 43#include "cpu/thread_context.hh" | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36#include "arch/alpha/pagetable.hh" 37#include "arch/alpha/tlb.hh" 38#include "arch/alpha/faults.hh" 39#include "base/inifile.hh" 40#include "base/str.hh" 41#include "base/trace.hh" 42#include "config/alpha_tlaser.hh" 43#include "cpu/thread_context.hh" |
44#include "params/AlphaDTB.hh" 45#include "params/AlphaITB.hh" | |
46 47using namespace std; 48using namespace EV5; 49 50namespace AlphaISA { 51/////////////////////////////////////////////////////////////////////// 52// 53// Alpha TLB 54// 55#ifdef DEBUG 56bool uncacheBit39 = false; 57bool uncacheBit40 = false; 58#endif 59 60#define MODE2MASK(X) (1 << (X)) 61 | 44 45using namespace std; 46using namespace EV5; 47 48namespace AlphaISA { 49/////////////////////////////////////////////////////////////////////// 50// 51// Alpha TLB 52// 53#ifdef DEBUG 54bool uncacheBit39 = false; 55bool uncacheBit40 = false; 56#endif 57 58#define MODE2MASK(X) (1 << (X)) 59 |
62TLB::TLB(const string &name, int s) 63 : SimObject(name), size(s), nlu(0) | 60TLB::TLB(const Params *p) 61 : SimObject(p), size(p->size), nlu(0) |
64{ 65 table = new TlbEntry[size]; 66 memset(table, 0, sizeof(TlbEntry[size])); 67 flushCache(); 68} 69 70TLB::~TLB() 71{ --- 209 unchanged lines hidden (view full) --- 281 } 282} 283 284 285/////////////////////////////////////////////////////////////////////// 286// 287// Alpha ITB 288// | 62{ 63 table = new TlbEntry[size]; 64 memset(table, 0, sizeof(TlbEntry[size])); 65 flushCache(); 66} 67 68TLB::~TLB() 69{ --- 209 unchanged lines hidden (view full) --- 279 } 280} 281 282 283/////////////////////////////////////////////////////////////////////// 284// 285// Alpha ITB 286// |
289ITB::ITB(const std::string &name, int size) 290 : TLB(name, size) | 287ITB::ITB(const Params *p) 288 : TLB(p) |
291{} 292 293 294void 295ITB::regStats() 296{ 297 hits 298 .name(name() + ".hits") --- 96 unchanged lines hidden (view full) --- 395 return checkCacheability(req); 396 397} 398 399/////////////////////////////////////////////////////////////////////// 400// 401// Alpha DTB 402// | 289{} 290 291 292void 293ITB::regStats() 294{ 295 hits 296 .name(name() + ".hits") --- 96 unchanged lines hidden (view full) --- 393 return checkCacheability(req); 394 395} 396 397/////////////////////////////////////////////////////////////////////// 398// 399// Alpha DTB 400// |
403 DTB::DTB(const std::string &name, int size) 404 : TLB(name, size) | 401 DTB::DTB(const Params *p) 402 : TLB(p) |
405{} 406 407void 408DTB::regStats() 409{ 410 read_hits 411 .name(name() + ".read_hits") 412 .desc("DTB read hits") --- 206 unchanged lines hidden (view full) --- 619 return *entry; 620} 621 622/* end namespace AlphaISA */ } 623 624AlphaISA::ITB * 625AlphaITBParams::create() 626{ | 403{} 404 405void 406DTB::regStats() 407{ 408 read_hits 409 .name(name() + ".read_hits") 410 .desc("DTB read hits") --- 206 unchanged lines hidden (view full) --- 617 return *entry; 618} 619 620/* end namespace AlphaISA */ } 621 622AlphaISA::ITB * 623AlphaITBParams::create() 624{ |
627 return new AlphaISA::ITB(name, size); | 625 return new AlphaISA::ITB(this); |
628} 629 630AlphaISA::DTB * 631AlphaDTBParams::create() 632{ | 626} 627 628AlphaISA::DTB * 629AlphaDTBParams::create() 630{ |
633 return new AlphaISA::DTB(name, size); | 631 return new AlphaISA::DTB(this); |
634} | 632} |