tlb.cc (4465:70123ac99284) tlb.cc (4762:c94e103c83ad)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "arch/alpha/pagetable.hh"
37#include "arch/alpha/tlb.hh"
38#include "arch/alpha/faults.hh"
39#include "base/inifile.hh"
40#include "base/str.hh"
41#include "base/trace.hh"
42#include "config/alpha_tlaser.hh"
43#include "cpu/thread_context.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "arch/alpha/pagetable.hh"
37#include "arch/alpha/tlb.hh"
38#include "arch/alpha/faults.hh"
39#include "base/inifile.hh"
40#include "base/str.hh"
41#include "base/trace.hh"
42#include "config/alpha_tlaser.hh"
43#include "cpu/thread_context.hh"
44#include "sim/builder.hh"
44#include "params/AlphaDTB.hh"
45#include "params/AlphaITB.hh"
45
46using namespace std;
47using namespace EV5;
48
49namespace AlphaISA {
50///////////////////////////////////////////////////////////////////////
51//
52// Alpha TLB

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595 if (advance)
596 nextnlu();
597
598 return *pte;
599}
600
601/* end namespace AlphaISA */ }
602
46
47using namespace std;
48using namespace EV5;
49
50namespace AlphaISA {
51///////////////////////////////////////////////////////////////////////
52//
53// Alpha TLB

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596 if (advance)
597 nextnlu();
598
599 return *pte;
600}
601
602/* end namespace AlphaISA */ }
603
603DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
604
605BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
606
607 Param<int> size;
608
609END_DECLARE_SIM_OBJECT_PARAMS(ITB)
610
611BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
612
613 INIT_PARAM_DFLT(size, "TLB size", 48)
614
615END_INIT_SIM_OBJECT_PARAMS(ITB)
616
617
618CREATE_SIM_OBJECT(ITB)
604AlphaISA::ITB *
605AlphaITBParams::create()
619{
606{
620 return new ITB(getInstanceName(), size);
607 return new AlphaISA::ITB(name, size);
621}
622
608}
609
623REGISTER_SIM_OBJECT("AlphaITB", ITB)
624
625BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
626
627 Param<int> size;
628
629END_DECLARE_SIM_OBJECT_PARAMS(DTB)
630
631BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
632
633 INIT_PARAM_DFLT(size, "TLB size", 64)
634
635END_INIT_SIM_OBJECT_PARAMS(DTB)
636
637
638CREATE_SIM_OBJECT(DTB)
610AlphaISA::DTB *
611AlphaDTBParams::create()
639{
612{
640 return new DTB(getInstanceName(), size);
613 return new AlphaISA::DTB(name, size);
641}
614}
642
643REGISTER_SIM_OBJECT("AlphaDTB", DTB)