tlb.cc (4088:a60eb44ae415) tlb.cc (4172:141705d83494)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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307 acv++;
308 return new ItbAcvFault(req->getVaddr());
309 }
310
311
312 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
313 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
314#if ALPHA_TLASER
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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307 acv++;
308 return new ItbAcvFault(req->getVaddr());
309 }
310
311
312 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
313 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
314#if ALPHA_TLASER
315 if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
315 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
316 VAddrSpaceEV5(req->getVaddr()) == 2)
317#else
318 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
319#endif
320 {
321 // only valid in kernel mode
316 VAddrSpaceEV5(req->getVaddr()) == 2)
317#else
318 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
319#endif
320 {
321 // only valid in kernel mode
322 if (ICM_CM(tc->readMiscReg(IPR_ICM)) !=
322 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
323 mode_kernel) {
324 acv++;
325 return new ItbAcvFault(req->getVaddr());
326 }
327
328 req->setPaddr(req->getVaddr() & PAddrImplMask);
329
330#if !ALPHA_TLASER
331 // sign extend the physical address properly
332 if (req->getPaddr() & PAddrUncachedBit40)
333 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
334 else
335 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
336#endif
337
338 } else {
339 // not a physical address: need to look up pte
323 mode_kernel) {
324 acv++;
325 return new ItbAcvFault(req->getVaddr());
326 }
327
328 req->setPaddr(req->getVaddr() & PAddrImplMask);
329
330#if !ALPHA_TLASER
331 // sign extend the physical address properly
332 if (req->getPaddr() & PAddrUncachedBit40)
333 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
334 else
335 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
336#endif
337
338 } else {
339 // not a physical address: need to look up pte
340 int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
340 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
341 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
342 asn);
343
344 if (!pte) {
345 misses++;
346 return new ItbPageFault(req->getVaddr());
347 }
348
349 req->setPaddr((pte->ppn << PageShift) +
350 (VAddr(req->getVaddr()).offset()
351 & ~3));
352
353 // check permissions for this access
354 if (!(pte->xre &
341 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
342 asn);
343
344 if (!pte) {
345 misses++;
346 return new ItbPageFault(req->getVaddr());
347 }
348
349 req->setPaddr((pte->ppn << PageShift) +
350 (VAddr(req->getVaddr()).offset()
351 & ~3));
352
353 // check permissions for this access
354 if (!(pte->xre &
355 (1 << ICM_CM(tc->readMiscReg(IPR_ICM))))) {
355 (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
356 // instruction access fault
357 acv++;
358 return new ItbAcvFault(req->getVaddr());
359 }
360
361 hits++;
362 }
363 }

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448}
449
450Fault
451DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
452{
453 Addr pc = tc->readPC();
454
455 mode_type mode =
356 // instruction access fault
357 acv++;
358 return new ItbAcvFault(req->getVaddr());
359 }
360
361 hits++;
362 }
363 }

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448}
449
450Fault
451DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
452{
453 Addr pc = tc->readPC();
454
455 mode_type mode =
456 (mode_type)DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM));
456 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
457
458
459 /**
460 * Check for alignment faults
461 */
462 if (req->getVaddr() & (req->getSize() - 1)) {
463 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
464 req->getSize());
465 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
466 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
467 }
468
469 if (PcPAL(pc)) {
470 mode = (req->getFlags() & ALTMODE) ?
471 (mode_type)ALT_MODE_AM(
457
458
459 /**
460 * Check for alignment faults
461 */
462 if (req->getVaddr() & (req->getSize() - 1)) {
463 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
464 req->getSize());
465 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
466 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
467 }
468
469 if (PcPAL(pc)) {
470 mode = (req->getFlags() & ALTMODE) ?
471 (mode_type)ALT_MODE_AM(
472 tc->readMiscReg(IPR_ALT_MODE))
472 tc->readMiscRegNoEffect(IPR_ALT_MODE))
473 : mode_kernel;
474 }
475
476 if (req->getFlags() & PHYSICAL) {
477 req->setPaddr(req->getVaddr());
478 } else {
479 // verify that this is a good virtual address
480 if (!validVirtualAddress(req->getVaddr())) {
481 if (write) { write_acv++; } else { read_acv++; }
482 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
483 MM_STAT_BAD_VA_MASK |
484 MM_STAT_ACV_MASK;
485 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
486 }
487
488 // Check for "superpage" mapping
489#if ALPHA_TLASER
473 : mode_kernel;
474 }
475
476 if (req->getFlags() & PHYSICAL) {
477 req->setPaddr(req->getVaddr());
478 } else {
479 // verify that this is a good virtual address
480 if (!validVirtualAddress(req->getVaddr())) {
481 if (write) { write_acv++; } else { read_acv++; }
482 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
483 MM_STAT_BAD_VA_MASK |
484 MM_STAT_ACV_MASK;
485 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
486 }
487
488 // Check for "superpage" mapping
489#if ALPHA_TLASER
490 if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
490 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
491 VAddrSpaceEV5(req->getVaddr()) == 2)
492#else
493 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
494#endif
495 {
496
497 // only valid in kernel mode
491 VAddrSpaceEV5(req->getVaddr()) == 2)
492#else
493 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
494#endif
495 {
496
497 // only valid in kernel mode
498 if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) !=
498 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
499 mode_kernel) {
500 if (write) { write_acv++; } else { read_acv++; }
501 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
502 MM_STAT_ACV_MASK);
503 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
504 }
505
506 req->setPaddr(req->getVaddr() & PAddrImplMask);

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514#endif
515
516 } else {
517 if (write)
518 write_accesses++;
519 else
520 read_accesses++;
521
499 mode_kernel) {
500 if (write) { write_acv++; } else { read_acv++; }
501 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
502 MM_STAT_ACV_MASK);
503 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
504 }
505
506 req->setPaddr(req->getVaddr() & PAddrImplMask);

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514#endif
515
516 } else {
517 if (write)
518 write_accesses++;
519 else
520 read_accesses++;
521
522 int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
522 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
523
524 // not a physical address: need to look up pte
525 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
526 asn);
527
528 if (!pte) {
529 // page fault
530 if (write) { write_misses++; } else { read_misses++; }

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524 // not a physical address: need to look up pte
525 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
526 asn);
527
528 if (!pte) {
529 // page fault
530 if (write) { write_misses++; } else { read_misses++; }

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