tlb.cc (3838:3d0e174a9d2b) | tlb.cc (4088:a60eb44ae415) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 32 unchanged lines hidden (view full) --- 41#include "base/trace.hh" 42#include "config/alpha_tlaser.hh" 43#include "cpu/thread_context.hh" 44#include "sim/builder.hh" 45 46using namespace std; 47using namespace EV5; 48 | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 32 unchanged lines hidden (view full) --- 41#include "base/trace.hh" 42#include "config/alpha_tlaser.hh" 43#include "cpu/thread_context.hh" 44#include "sim/builder.hh" 45 46using namespace std; 47using namespace EV5; 48 |
49namespace AlphaISA 50{ | 49namespace AlphaISA { |
51/////////////////////////////////////////////////////////////////////// 52// 53// Alpha TLB 54// 55#ifdef DEBUG 56bool uncacheBit39 = false; 57bool uncacheBit40 = false; 58#endif --- 52 unchanged lines hidden (view full) --- 111 * The Turbolaser platform (and EV5) support having the bit in 39, but 112 * Tsunami (which Linux assumes uses an EV6) generates accesses with 113 * the bit in 40. So we must check for both, but we have debug flags 114 * to catch a weird case where both are used, which shouldn't happen. 115 */ 116 117 118#if ALPHA_TLASER | 50/////////////////////////////////////////////////////////////////////// 51// 52// Alpha TLB 53// 54#ifdef DEBUG 55bool uncacheBit39 = false; 56bool uncacheBit40 = false; 57#endif --- 52 unchanged lines hidden (view full) --- 110 * The Turbolaser platform (and EV5) support having the bit in 39, but 111 * Tsunami (which Linux assumes uses an EV6) generates accesses with 112 * the bit in 40. So we must check for both, but we have debug flags 113 * to catch a weird case where both are used, which shouldn't happen. 114 */ 115 116 117#if ALPHA_TLASER |
119 if (req->getPaddr() & PAddrUncachedBit39) { | 118 if (req->getPaddr() & PAddrUncachedBit39) |
120#else | 119#else |
121 if (req->getPaddr() & PAddrUncachedBit43) { | 120 if (req->getPaddr() & PAddrUncachedBit43) |
122#endif | 121#endif |
122 { |
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123 // IPR memory space not implemented 124 if (PAddrIprSpace(req->getPaddr())) { 125 return new UnimpFault("IPR memory space not implemented!"); 126 } else { 127 // mark request as uncacheable 128 req->setFlags(req->getFlags() | UNCACHEABLE); 129 130#if !ALPHA_TLASER --- 177 unchanged lines hidden (view full) --- 308 return new ItbAcvFault(req->getVaddr()); 309 } 310 311 312 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 313 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 314#if ALPHA_TLASER 315 if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && | 123 // IPR memory space not implemented 124 if (PAddrIprSpace(req->getPaddr())) { 125 return new UnimpFault("IPR memory space not implemented!"); 126 } else { 127 // mark request as uncacheable 128 req->setFlags(req->getFlags() | UNCACHEABLE); 129 130#if !ALPHA_TLASER --- 177 unchanged lines hidden (view full) --- 308 return new ItbAcvFault(req->getVaddr()); 309 } 310 311 312 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 313 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 314#if ALPHA_TLASER 315 if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && |
316 VAddrSpaceEV5(req->getVaddr()) == 2) { | 316 VAddrSpaceEV5(req->getVaddr()) == 2) |
317#else | 317#else |
318 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { | 318 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) |
319#endif | 319#endif |
320 { |
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320 // only valid in kernel mode 321 if (ICM_CM(tc->readMiscReg(IPR_ICM)) != 322 mode_kernel) { 323 acv++; 324 return new ItbAcvFault(req->getVaddr()); 325 } 326 327 req->setPaddr(req->getVaddr() & PAddrImplMask); --- 154 unchanged lines hidden (view full) --- 482 MM_STAT_BAD_VA_MASK | 483 MM_STAT_ACV_MASK; 484 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 485 } 486 487 // Check for "superpage" mapping 488#if ALPHA_TLASER 489 if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && | 321 // only valid in kernel mode 322 if (ICM_CM(tc->readMiscReg(IPR_ICM)) != 323 mode_kernel) { 324 acv++; 325 return new ItbAcvFault(req->getVaddr()); 326 } 327 328 req->setPaddr(req->getVaddr() & PAddrImplMask); --- 154 unchanged lines hidden (view full) --- 483 MM_STAT_BAD_VA_MASK | 484 MM_STAT_ACV_MASK; 485 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 486 } 487 488 // Check for "superpage" mapping 489#if ALPHA_TLASER 490 if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && |
490 VAddrSpaceEV5(req->getVaddr()) == 2) { | 491 VAddrSpaceEV5(req->getVaddr()) == 2) |
491#else | 492#else |
492 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { | 493 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) |
493#endif | 494#endif |
495 { |
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494 495 // only valid in kernel mode 496 if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) != 497 mode_kernel) { 498 if (write) { write_acv++; } else { read_acv++; } 499 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 500 MM_STAT_ACV_MASK); 501 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); --- 85 unchanged lines hidden (view full) --- 587 PTE *pte = &table[nlu]; 588 589 if (advance) 590 nextnlu(); 591 592 return *pte; 593} 594 | 496 497 // only valid in kernel mode 498 if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) != 499 mode_kernel) { 500 if (write) { write_acv++; } else { read_acv++; } 501 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 502 MM_STAT_ACV_MASK); 503 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); --- 85 unchanged lines hidden (view full) --- 589 PTE *pte = &table[nlu]; 590 591 if (advance) 592 nextnlu(); 593 594 return *pte; 595} 596 |
597/* end namespace AlphaISA */ } 598 |
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595DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB) 596 597BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 598 599 Param<int> size; 600 601END_DECLARE_SIM_OBJECT_PARAMS(ITB) 602 --- 25 unchanged lines hidden (view full) --- 628 629 630CREATE_SIM_OBJECT(DTB) 631{ 632 return new DTB(getInstanceName(), size); 633} 634 635REGISTER_SIM_OBJECT("AlphaDTB", DTB) | 599DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB) 600 601BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 602 603 Param<int> size; 604 605END_DECLARE_SIM_OBJECT_PARAMS(ITB) 606 --- 25 unchanged lines hidden (view full) --- 632 633 634CREATE_SIM_OBJECT(DTB) 635{ 636 return new DTB(getInstanceName(), size); 637} 638 639REGISTER_SIM_OBJECT("AlphaDTB", DTB) |
636} | |