tlb.cc (2984:797622d7b311) | tlb.cc (3453:c3ce58882751) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 32 unchanged lines hidden (view full) --- 41#include "base/trace.hh" 42#include "config/alpha_tlaser.hh" 43#include "cpu/thread_context.hh" 44#include "sim/builder.hh" 45 46using namespace std; 47using namespace EV5; 48 | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 32 unchanged lines hidden (view full) --- 41#include "base/trace.hh" 42#include "config/alpha_tlaser.hh" 43#include "cpu/thread_context.hh" 44#include "sim/builder.hh" 45 46using namespace std; 47using namespace EV5; 48 |
49/////////////////////////////////////////////////////////////////////// 50// 51// Alpha TLB 52// | 49namespace AlphaISA 50{ 51 /////////////////////////////////////////////////////////////////////// 52 // 53 // Alpha TLB 54 // |
53#ifdef DEBUG | 55#ifdef DEBUG |
54bool uncacheBit39 = false; 55bool uncacheBit40 = false; | 56 bool uncacheBit39 = false; 57 bool uncacheBit40 = false; |
56#endif 57 58#define MODE2MASK(X) (1 << (X)) 59 | 58#endif 59 60#define MODE2MASK(X) (1 << (X)) 61 |
60AlphaTLB::AlphaTLB(const string &name, int s) 61 : SimObject(name), size(s), nlu(0) 62{ 63 table = new AlphaISA::PTE[size]; 64 memset(table, 0, sizeof(AlphaISA::PTE[size])); 65} | 62 TLB::TLB(const string &name, int s) 63 : SimObject(name), size(s), nlu(0) 64 { 65 table = new PTE[size]; 66 memset(table, 0, sizeof(PTE[size])); 67 } |
66 | 68 |
67AlphaTLB::~AlphaTLB() 68{ 69 if (table) 70 delete [] table; 71} | 69 TLB::~TLB() 70 { 71 if (table) 72 delete [] table; 73 } |
72 | 74 |
73// look up an entry in the TLB 74AlphaISA::PTE * 75AlphaTLB::lookup(Addr vpn, uint8_t asn) const 76{ 77 // assume not found... 78 AlphaISA::PTE *retval = NULL; | 75 // look up an entry in the TLB 76 PTE * 77 TLB::lookup(Addr vpn, uint8_t asn) const 78 { 79 // assume not found... 80 PTE *retval = NULL; |
79 | 81 |
80 PageTable::const_iterator i = lookupTable.find(vpn); 81 if (i != lookupTable.end()) { 82 while (i->first == vpn) { 83 int index = i->second; 84 AlphaISA::PTE *pte = &table[index]; 85 assert(pte->valid); 86 if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { 87 retval = pte; 88 break; 89 } | 82 PageTable::const_iterator i = lookupTable.find(vpn); 83 if (i != lookupTable.end()) { 84 while (i->first == vpn) { 85 int index = i->second; 86 PTE *pte = &table[index]; 87 assert(pte->valid); 88 if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { 89 retval = pte; 90 break; 91 } |
90 | 92 |
91 ++i; | 93 ++i; 94 } |
92 } | 95 } |
96 97 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 98 retval ? "hit" : "miss", retval ? retval->ppn : 0); 99 return retval; |
|
93 } 94 | 100 } 101 |
95 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 96 retval ? "hit" : "miss", retval ? retval->ppn : 0); 97 return retval; 98} | |
99 | 102 |
103 Fault 104 TLB::checkCacheability(RequestPtr &req) 105 { 106 // in Alpha, cacheability is controlled by upper-level bits of the 107 // physical address |
|
100 | 108 |
101Fault 102AlphaTLB::checkCacheability(RequestPtr &req) 103{ 104 // in Alpha, cacheability is controlled by upper-level bits of the 105 // physical address | 109 /* 110 * We support having the uncacheable bit in either bit 39 or bit 40. 111 * The Turbolaser platform (and EV5) support having the bit in 39, but 112 * Tsunami (which Linux assumes uses an EV6) generates accesses with 113 * the bit in 40. So we must check for both, but we have debug flags 114 * to catch a weird case where both are used, which shouldn't happen. 115 */ |
106 | 116 |
107 /* 108 * We support having the uncacheable bit in either bit 39 or bit 40. 109 * The Turbolaser platform (and EV5) support having the bit in 39, but 110 * Tsunami (which Linux assumes uses an EV6) generates accesses with 111 * the bit in 40. So we must check for both, but we have debug flags 112 * to catch a weird case where both are used, which shouldn't happen. 113 */ | |
114 | 117 |
115 | |
116#if ALPHA_TLASER | 118#if ALPHA_TLASER |
117 if (req->getPaddr() & PAddrUncachedBit39) { | 119 if (req->getPaddr() & PAddrUncachedBit39) { |
118#else | 120#else |
119 if (req->getPaddr() & PAddrUncachedBit43) { | 121 if (req->getPaddr() & PAddrUncachedBit43) { |
120#endif | 122#endif |
121 // IPR memory space not implemented 122 if (PAddrIprSpace(req->getPaddr())) { 123 return new UnimpFault("IPR memory space not implemented!"); 124 } else { 125 // mark request as uncacheable 126 req->setFlags(req->getFlags() | UNCACHEABLE); | 123 // IPR memory space not implemented 124 if (PAddrIprSpace(req->getPaddr())) { 125 return new UnimpFault("IPR memory space not implemented!"); 126 } else { 127 // mark request as uncacheable 128 req->setFlags(req->getFlags() | UNCACHEABLE); |
127 128#if !ALPHA_TLASER | 129 130#if !ALPHA_TLASER |
129 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 130 req->setPaddr(req->getPaddr() & PAddrUncachedMask); | 131 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 132 req->setPaddr(req->getPaddr() & PAddrUncachedMask); |
131#endif | 133#endif |
134 } |
|
132 } | 135 } |
136 return NoFault; |
|
133 } | 137 } |
134 return NoFault; 135} | |
136 137 | 138 139 |
138// insert a new TLB entry 139void 140AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte) 141{ 142 AlphaISA::VAddr vaddr = addr; 143 if (table[nlu].valid) { 144 Addr oldvpn = table[nlu].tag; 145 PageTable::iterator i = lookupTable.find(oldvpn); | 140 // insert a new TLB entry 141 void 142 TLB::insert(Addr addr, PTE &pte) 143 { 144 VAddr vaddr = addr; 145 if (table[nlu].valid) { 146 Addr oldvpn = table[nlu].tag; 147 PageTable::iterator i = lookupTable.find(oldvpn); |
146 | 148 |
147 if (i == lookupTable.end()) 148 panic("TLB entry not found in lookupTable"); 149 150 int index; 151 while ((index = i->second) != nlu) { 152 if (table[index].tag != oldvpn) | 149 if (i == lookupTable.end()) |
153 panic("TLB entry not found in lookupTable"); 154 | 150 panic("TLB entry not found in lookupTable"); 151 |
155 ++i; 156 } | 152 int index; 153 while ((index = i->second) != nlu) { 154 if (table[index].tag != oldvpn) 155 panic("TLB entry not found in lookupTable"); |
157 | 156 |
158 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); | 157 ++i; 158 } |
159 | 159 |
160 lookupTable.erase(i); 161 } | 160 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); |
162 | 161 |
163 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); | 162 lookupTable.erase(i); 163 } |
164 | 164 |
165 table[nlu] = pte; 166 table[nlu].tag = vaddr.vpn(); 167 table[nlu].valid = true; | 165 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); |
168 | 166 |
169 lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 170 nextnlu(); 171} | 167 table[nlu] = pte; 168 table[nlu].tag = vaddr.vpn(); 169 table[nlu].valid = true; |
172 | 170 |
173void 174AlphaTLB::flushAll() 175{ 176 DPRINTF(TLB, "flushAll\n"); 177 memset(table, 0, sizeof(AlphaISA::PTE[size])); 178 lookupTable.clear(); 179 nlu = 0; 180} | 171 lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 172 nextnlu(); 173 } |
181 | 174 |
182void 183AlphaTLB::flushProcesses() 184{ 185 PageTable::iterator i = lookupTable.begin(); 186 PageTable::iterator end = lookupTable.end(); 187 while (i != end) { 188 int index = i->second; 189 AlphaISA::PTE *pte = &table[index]; 190 assert(pte->valid); | 175 void 176 TLB::flushAll() 177 { 178 DPRINTF(TLB, "flushAll\n"); 179 memset(table, 0, sizeof(PTE[size])); 180 lookupTable.clear(); 181 nlu = 0; 182 } |
191 | 183 |
192 // we can't increment i after we erase it, so save a copy and 193 // increment it to get the next entry now 194 PageTable::iterator cur = i; 195 ++i; | 184 void 185 TLB::flushProcesses() 186 { 187 PageTable::iterator i = lookupTable.begin(); 188 PageTable::iterator end = lookupTable.end(); 189 while (i != end) { 190 int index = i->second; 191 PTE *pte = &table[index]; 192 assert(pte->valid); |
196 | 193 |
197 if (!pte->asma) { 198 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); 199 pte->valid = false; 200 lookupTable.erase(cur); | 194 // we can't increment i after we erase it, so save a copy and 195 // increment it to get the next entry now 196 PageTable::iterator cur = i; 197 ++i; 198 199 if (!pte->asma) { 200 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); 201 pte->valid = false; 202 lookupTable.erase(cur); 203 } |
201 } 202 } | 204 } 205 } |
203} | |
204 | 206 |
205void 206AlphaTLB::flushAddr(Addr addr, uint8_t asn) 207{ 208 AlphaISA::VAddr vaddr = addr; | 207 void 208 TLB::flushAddr(Addr addr, uint8_t asn) 209 { 210 VAddr vaddr = addr; |
209 | 211 |
210 PageTable::iterator i = lookupTable.find(vaddr.vpn()); 211 if (i == lookupTable.end()) 212 return; | 212 PageTable::iterator i = lookupTable.find(vaddr.vpn()); 213 if (i == lookupTable.end()) 214 return; |
213 | 215 |
214 while (i->first == vaddr.vpn()) { 215 int index = i->second; 216 AlphaISA::PTE *pte = &table[index]; 217 assert(pte->valid); | 216 while (i->first == vaddr.vpn()) { 217 int index = i->second; 218 PTE *pte = &table[index]; 219 assert(pte->valid); |
218 | 220 |
219 if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { 220 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 221 pte->ppn); | 221 if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { 222 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 223 pte->ppn); |
222 | 224 |
223 // invalidate this entry 224 pte->valid = false; | 225 // invalidate this entry 226 pte->valid = false; |
225 | 227 |
226 lookupTable.erase(i); 227 } | 228 lookupTable.erase(i); 229 } |
228 | 230 |
229 ++i; | 231 ++i; 232 } |
230 } | 233 } |
231} | |
232 233 | 234 235 |
234void 235AlphaTLB::serialize(ostream &os) 236{ 237 SERIALIZE_SCALAR(size); 238 SERIALIZE_SCALAR(nlu); | 236 void 237 TLB::serialize(ostream &os) 238 { 239 SERIALIZE_SCALAR(size); 240 SERIALIZE_SCALAR(nlu); |
239 | 241 |
240 for (int i = 0; i < size; i++) { 241 nameOut(os, csprintf("%s.PTE%d", name(), i)); 242 table[i].serialize(os); | 242 for (int i = 0; i < size; i++) { 243 nameOut(os, csprintf("%s.PTE%d", name(), i)); 244 table[i].serialize(os); 245 } |
243 } | 246 } |
244} | |
245 | 247 |
246void 247AlphaTLB::unserialize(Checkpoint *cp, const string §ion) 248{ 249 UNSERIALIZE_SCALAR(size); 250 UNSERIALIZE_SCALAR(nlu); | 248 void 249 TLB::unserialize(Checkpoint *cp, const string §ion) 250 { 251 UNSERIALIZE_SCALAR(size); 252 UNSERIALIZE_SCALAR(nlu); |
251 | 253 |
252 for (int i = 0; i < size; i++) { 253 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 254 if (table[i].valid) { 255 lookupTable.insert(make_pair(table[i].tag, i)); | 254 for (int i = 0; i < size; i++) { 255 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 256 if (table[i].valid) { 257 lookupTable.insert(make_pair(table[i].tag, i)); 258 } |
256 } 257 } | 259 } 260 } |
258} | |
259 260 | 261 262 |
261/////////////////////////////////////////////////////////////////////// 262// 263// Alpha ITB 264// 265AlphaITB::AlphaITB(const std::string &name, int size) 266 : AlphaTLB(name, size) 267{} | 263 /////////////////////////////////////////////////////////////////////// 264 // 265 // Alpha ITB 266 // 267 ITB::ITB(const std::string &name, int size) 268 : TLB(name, size) 269 {} |
268 269 | 270 271 |
270void 271AlphaITB::regStats() 272{ 273 hits 274 .name(name() + ".hits") 275 .desc("ITB hits"); 276 misses 277 .name(name() + ".misses") 278 .desc("ITB misses"); 279 acv 280 .name(name() + ".acv") 281 .desc("ITB acv"); 282 accesses 283 .name(name() + ".accesses") 284 .desc("ITB accesses"); | 272 void 273 ITB::regStats() 274 { 275 hits 276 .name(name() + ".hits") 277 .desc("ITB hits"); 278 misses 279 .name(name() + ".misses") 280 .desc("ITB misses"); 281 acv 282 .name(name() + ".acv") 283 .desc("ITB acv"); 284 accesses 285 .name(name() + ".accesses") 286 .desc("ITB accesses"); |
285 | 287 |
286 accesses = hits + misses; 287} 288 289 290Fault 291AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const 292{ 293 if (AlphaISA::PcPAL(req->getVaddr())) { 294 // strip off PAL PC marker (lsb is 1) 295 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 296 hits++; 297 return NoFault; | 288 accesses = hits + misses; |
298 } 299 | 289 } 290 |
300 if (req->getFlags() & PHYSICAL) { 301 req->setPaddr(req->getVaddr()); 302 } else { 303 // verify that this is a good virtual address 304 if (!validVirtualAddress(req->getVaddr())) { 305 acv++; 306 return new ItbAcvFault(req->getVaddr()); | 291 292 Fault 293 ITB::translate(RequestPtr &req, ThreadContext *tc) const 294 { 295 if (PcPAL(req->getVaddr())) { 296 // strip off PAL PC marker (lsb is 1) 297 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 298 hits++; 299 return NoFault; |
307 } 308 | 300 } 301 |
302 if (req->getFlags() & PHYSICAL) { 303 req->setPaddr(req->getVaddr()); 304 } else { 305 // verify that this is a good virtual address 306 if (!validVirtualAddress(req->getVaddr())) { 307 acv++; 308 return new ItbAcvFault(req->getVaddr()); 309 } |
|
309 | 310 |
310 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 311 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 | 311 312 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 313 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 |
312#if ALPHA_TLASER | 314#if ALPHA_TLASER |
313 if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && 314 VAddrSpaceEV5(req->getVaddr()) == 2) { | 315 if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && 316 VAddrSpaceEV5(req->getVaddr()) == 2) { |
315#else | 317#else |
316 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { | 318 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { |
317#endif | 319#endif |
318 // only valid in kernel mode 319 if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) != 320 AlphaISA::mode_kernel) { 321 acv++; 322 return new ItbAcvFault(req->getVaddr()); 323 } | 320 // only valid in kernel mode 321 if (ICM_CM(tc->readMiscReg(IPR_ICM)) != 322 mode_kernel) { 323 acv++; 324 return new ItbAcvFault(req->getVaddr()); 325 } |
324 | 326 |
325 req->setPaddr(req->getVaddr() & PAddrImplMask); | 327 req->setPaddr(req->getVaddr() & PAddrImplMask); |
326 327#if !ALPHA_TLASER | 328 329#if !ALPHA_TLASER |
328 // sign extend the physical address properly 329 if (req->getPaddr() & PAddrUncachedBit40) 330 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 331 else 332 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); | 330 // sign extend the physical address properly 331 if (req->getPaddr() & PAddrUncachedBit40) 332 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 333 else 334 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); |
333#endif 334 | 335#endif 336 |
335 } else { 336 // not a physical address: need to look up pte 337 int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN)); 338 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), 339 asn); | 337 } else { 338 // not a physical address: need to look up pte 339 int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN)); 340 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), 341 asn); |
340 | 342 |
341 if (!pte) { 342 misses++; 343 return new ItbPageFault(req->getVaddr()); 344 } | 343 if (!pte) { 344 misses++; 345 return new ItbPageFault(req->getVaddr()); 346 } |
345 | 347 |
346 req->setPaddr((pte->ppn << AlphaISA::PageShift) + 347 (AlphaISA::VAddr(req->getVaddr()).offset() 348 & ~3)); | 348 req->setPaddr((pte->ppn << PageShift) + 349 (VAddr(req->getVaddr()).offset() 350 & ~3)); |
349 | 351 |
350 // check permissions for this access 351 if (!(pte->xre & 352 (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) { 353 // instruction access fault 354 acv++; 355 return new ItbAcvFault(req->getVaddr()); 356 } | 352 // check permissions for this access 353 if (!(pte->xre & 354 (1 << ICM_CM(tc->readMiscReg(IPR_ICM))))) { 355 // instruction access fault 356 acv++; 357 return new ItbAcvFault(req->getVaddr()); 358 } |
357 | 359 |
358 hits++; | 360 hits++; 361 } |
359 } | 362 } |
360 } | |
361 | 363 |
362 // check that the physical address is ok (catch bad physical addresses) 363 if (req->getPaddr() & ~PAddrImplMask) 364 return genMachineCheckFault(); | 364 // check that the physical address is ok (catch bad physical addresses) 365 if (req->getPaddr() & ~PAddrImplMask) 366 return genMachineCheckFault(); |
365 | 367 |
366 return checkCacheability(req); | 368 return checkCacheability(req); |
367 | 369 |
368} | 370 } |
369 | 371 |
370/////////////////////////////////////////////////////////////////////// 371// 372// Alpha DTB 373// 374AlphaDTB::AlphaDTB(const std::string &name, int size) 375 : AlphaTLB(name, size) 376{} | 372 /////////////////////////////////////////////////////////////////////// 373 // 374 // Alpha DTB 375 // 376 DTB::DTB(const std::string &name, int size) 377 : TLB(name, size) 378 {} |
377 | 379 |
378void 379AlphaDTB::regStats() 380{ 381 read_hits 382 .name(name() + ".read_hits") 383 .desc("DTB read hits") 384 ; | 380 void 381 DTB::regStats() 382 { 383 read_hits 384 .name(name() + ".read_hits") 385 .desc("DTB read hits") 386 ; |
385 | 387 |
386 read_misses 387 .name(name() + ".read_misses") 388 .desc("DTB read misses") 389 ; | 388 read_misses 389 .name(name() + ".read_misses") 390 .desc("DTB read misses") 391 ; |
390 | 392 |
391 read_acv 392 .name(name() + ".read_acv") 393 .desc("DTB read access violations") 394 ; | 393 read_acv 394 .name(name() + ".read_acv") 395 .desc("DTB read access violations") 396 ; |
395 | 397 |
396 read_accesses 397 .name(name() + ".read_accesses") 398 .desc("DTB read accesses") 399 ; | 398 read_accesses 399 .name(name() + ".read_accesses") 400 .desc("DTB read accesses") 401 ; |
400 | 402 |
401 write_hits 402 .name(name() + ".write_hits") 403 .desc("DTB write hits") 404 ; | 403 write_hits 404 .name(name() + ".write_hits") 405 .desc("DTB write hits") 406 ; |
405 | 407 |
406 write_misses 407 .name(name() + ".write_misses") 408 .desc("DTB write misses") 409 ; | 408 write_misses 409 .name(name() + ".write_misses") 410 .desc("DTB write misses") 411 ; |
410 | 412 |
411 write_acv 412 .name(name() + ".write_acv") 413 .desc("DTB write access violations") 414 ; | 413 write_acv 414 .name(name() + ".write_acv") 415 .desc("DTB write access violations") 416 ; |
415 | 417 |
416 write_accesses 417 .name(name() + ".write_accesses") 418 .desc("DTB write accesses") 419 ; | 418 write_accesses 419 .name(name() + ".write_accesses") 420 .desc("DTB write accesses") 421 ; |
420 | 422 |
421 hits 422 .name(name() + ".hits") 423 .desc("DTB hits") 424 ; | 423 hits 424 .name(name() + ".hits") 425 .desc("DTB hits") 426 ; |
425 | 427 |
426 misses 427 .name(name() + ".misses") 428 .desc("DTB misses") 429 ; | 428 misses 429 .name(name() + ".misses") 430 .desc("DTB misses") 431 ; |
430 | 432 |
431 acv 432 .name(name() + ".acv") 433 .desc("DTB access violations") 434 ; | 433 acv 434 .name(name() + ".acv") 435 .desc("DTB access violations") 436 ; |
435 | 437 |
436 accesses 437 .name(name() + ".accesses") 438 .desc("DTB accesses") 439 ; | 438 accesses 439 .name(name() + ".accesses") 440 .desc("DTB accesses") 441 ; |
440 | 442 |
441 hits = read_hits + write_hits; 442 misses = read_misses + write_misses; 443 acv = read_acv + write_acv; 444 accesses = read_accesses + write_accesses; 445} | 443 hits = read_hits + write_hits; 444 misses = read_misses + write_misses; 445 acv = read_acv + write_acv; 446 accesses = read_accesses + write_accesses; 447 } |
446 | 448 |
447Fault 448AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const 449{ 450 Addr pc = tc->readPC(); | 449 Fault 450 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const 451 { 452 Addr pc = tc->readPC(); |
451 | 453 |
452 AlphaISA::mode_type mode = 453 (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)); | 454 mode_type mode = 455 (mode_type)DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)); |
454 455 | 456 457 |
456 /** 457 * Check for alignment faults 458 */ 459 if (req->getVaddr() & (req->getSize() - 1)) { 460 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 461 req->getSize()); 462 uint64_t flags = write ? MM_STAT_WR_MASK : 0; 463 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 464 } | 458 /** 459 * Check for alignment faults 460 */ 461 if (req->getVaddr() & (req->getSize() - 1)) { 462 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 463 req->getSize()); 464 uint64_t flags = write ? MM_STAT_WR_MASK : 0; 465 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 466 } |
465 | 467 |
466 if (pc & 0x1) { 467 mode = (req->getFlags() & ALTMODE) ? 468 (AlphaISA::mode_type)ALT_MODE_AM( 469 tc->readMiscReg(AlphaISA::IPR_ALT_MODE)) 470 : AlphaISA::mode_kernel; 471 } 472 473 if (req->getFlags() & PHYSICAL) { 474 req->setPaddr(req->getVaddr()); 475 } else { 476 // verify that this is a good virtual address 477 if (!validVirtualAddress(req->getVaddr())) { 478 if (write) { write_acv++; } else { read_acv++; } 479 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 480 MM_STAT_BAD_VA_MASK | 481 MM_STAT_ACV_MASK; 482 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); | 468 if (pc & 0x1) { 469 mode = (req->getFlags() & ALTMODE) ? 470 (mode_type)ALT_MODE_AM( 471 tc->readMiscReg(IPR_ALT_MODE)) 472 : mode_kernel; |
483 } 484 | 473 } 474 |
485 // Check for "superpage" mapping | 475 if (req->getFlags() & PHYSICAL) { 476 req->setPaddr(req->getVaddr()); 477 } else { 478 // verify that this is a good virtual address 479 if (!validVirtualAddress(req->getVaddr())) { 480 if (write) { write_acv++; } else { read_acv++; } 481 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 482 MM_STAT_BAD_VA_MASK | 483 MM_STAT_ACV_MASK; 484 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 485 } 486 487 // Check for "superpage" mapping |
486#if ALPHA_TLASER | 488#if ALPHA_TLASER |
487 if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && 488 VAddrSpaceEV5(req->getVaddr()) == 2) { | 489 if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) && 490 VAddrSpaceEV5(req->getVaddr()) == 2) { |
489#else | 491#else |
490 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { | 492 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { |
491#endif 492 | 493#endif 494 |
493 // only valid in kernel mode 494 if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) != 495 AlphaISA::mode_kernel) { 496 if (write) { write_acv++; } else { read_acv++; } 497 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 498 MM_STAT_ACV_MASK); 499 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 500 } | 495 // only valid in kernel mode 496 if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) != 497 mode_kernel) { 498 if (write) { write_acv++; } else { read_acv++; } 499 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 500 MM_STAT_ACV_MASK); 501 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 502 } |
501 | 503 |
502 req->setPaddr(req->getVaddr() & PAddrImplMask); | 504 req->setPaddr(req->getVaddr() & PAddrImplMask); |
503 504#if !ALPHA_TLASER | 505 506#if !ALPHA_TLASER |
505 // sign extend the physical address properly 506 if (req->getPaddr() & PAddrUncachedBit40) 507 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 508 else 509 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); | 507 // sign extend the physical address properly 508 if (req->getPaddr() & PAddrUncachedBit40) 509 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 510 else 511 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); |
510#endif 511 | 512#endif 513 |
512 } else { 513 if (write) 514 write_accesses++; 515 else 516 read_accesses++; | 514 } else { 515 if (write) 516 write_accesses++; 517 else 518 read_accesses++; |
517 | 519 |
518 int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN)); | 520 int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN)); |
519 | 521 |
520 // not a physical address: need to look up pte 521 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), 522 asn); | 522 // not a physical address: need to look up pte 523 PTE *pte = lookup(VAddr(req->getVaddr()).vpn(), 524 asn); |
523 | 525 |
524 if (!pte) { 525 // page fault 526 if (write) { write_misses++; } else { read_misses++; } 527 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 528 MM_STAT_DTB_MISS_MASK; 529 return (req->getFlags() & VPTE) ? 530 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 531 flags)) : 532 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 533 flags)); 534 } | 526 if (!pte) { 527 // page fault 528 if (write) { write_misses++; } else { read_misses++; } 529 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 530 MM_STAT_DTB_MISS_MASK; 531 return (req->getFlags() & VPTE) ? 532 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 533 flags)) : 534 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 535 flags)); 536 } |
535 | 537 |
536 req->setPaddr((pte->ppn << AlphaISA::PageShift) + 537 AlphaISA::VAddr(req->getVaddr()).offset()); | 538 req->setPaddr((pte->ppn << PageShift) + 539 VAddr(req->getVaddr()).offset()); |
538 | 540 |
539 if (write) { 540 if (!(pte->xwe & MODE2MASK(mode))) { 541 // declare the instruction access fault 542 write_acv++; 543 uint64_t flags = MM_STAT_WR_MASK | 544 MM_STAT_ACV_MASK | 545 (pte->fonw ? MM_STAT_FONW_MASK : 0); 546 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); | 541 if (write) { 542 if (!(pte->xwe & MODE2MASK(mode))) { 543 // declare the instruction access fault 544 write_acv++; 545 uint64_t flags = MM_STAT_WR_MASK | 546 MM_STAT_ACV_MASK | 547 (pte->fonw ? MM_STAT_FONW_MASK : 0); 548 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 549 } 550 if (pte->fonw) { 551 write_acv++; 552 uint64_t flags = MM_STAT_WR_MASK | 553 MM_STAT_FONW_MASK; 554 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 555 } 556 } else { 557 if (!(pte->xre & MODE2MASK(mode))) { 558 read_acv++; 559 uint64_t flags = MM_STAT_ACV_MASK | 560 (pte->fonr ? MM_STAT_FONR_MASK : 0); 561 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 562 } 563 if (pte->fonr) { 564 read_acv++; 565 uint64_t flags = MM_STAT_FONR_MASK; 566 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 567 } |
547 } | 568 } |
548 if (pte->fonw) { 549 write_acv++; 550 uint64_t flags = MM_STAT_WR_MASK | 551 MM_STAT_FONW_MASK; 552 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 553 } 554 } else { 555 if (!(pte->xre & MODE2MASK(mode))) { 556 read_acv++; 557 uint64_t flags = MM_STAT_ACV_MASK | 558 (pte->fonr ? MM_STAT_FONR_MASK : 0); 559 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 560 } 561 if (pte->fonr) { 562 read_acv++; 563 uint64_t flags = MM_STAT_FONR_MASK; 564 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 565 } | |
566 } | 569 } |
570 571 if (write) 572 write_hits++; 573 else 574 read_hits++; |
|
567 } 568 | 575 } 576 |
569 if (write) 570 write_hits++; 571 else 572 read_hits++; | 577 // check that the physical address is ok (catch bad physical addresses) 578 if (req->getPaddr() & ~PAddrImplMask) 579 return genMachineCheckFault(); 580 581 return checkCacheability(req); |
573 } 574 | 582 } 583 |
575 // check that the physical address is ok (catch bad physical addresses) 576 if (req->getPaddr() & ~PAddrImplMask) 577 return genMachineCheckFault(); | 584 PTE & 585 TLB::index(bool advance) 586 { 587 PTE *pte = &table[nlu]; |
578 | 588 |
579 return checkCacheability(req); 580} | 589 if (advance) 590 nextnlu(); |
581 | 591 |
582AlphaISA::PTE & 583AlphaTLB::index(bool advance) 584{ 585 AlphaISA::PTE *pte = &table[nlu]; | 592 return *pte; 593 } |
586 | 594 |
587 if (advance) 588 nextnlu(); | 595 DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB) |
589 | 596 |
590 return *pte; 591} | 597 BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) |
592 | 598 |
593DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB) | 599 Param<int> size; |
594 | 600 |
595BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) | 601 END_DECLARE_SIM_OBJECT_PARAMS(ITB) |
596 | 602 |
597 Param<int> size; | 603 BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) |
598 | 604 |
599END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) | 605 INIT_PARAM_DFLT(size, "TLB size", 48) |
600 | 606 |
601BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB) | 607 END_INIT_SIM_OBJECT_PARAMS(ITB) |
602 | 608 |
603 INIT_PARAM_DFLT(size, "TLB size", 48) | |
604 | 609 |
605END_INIT_SIM_OBJECT_PARAMS(AlphaITB) | 610 CREATE_SIM_OBJECT(ITB) 611 { 612 return new ITB(getInstanceName(), size); 613 } |
606 | 614 |
615 REGISTER_SIM_OBJECT("AlphaITB", ITB) |
|
607 | 616 |
608CREATE_SIM_OBJECT(AlphaITB) 609{ 610 return new AlphaITB(getInstanceName(), size); 611} | 617 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) |
612 | 618 |
613REGISTER_SIM_OBJECT("AlphaITB", AlphaITB) | 619 Param<int> size; |
614 | 620 |
615BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) | 621 END_DECLARE_SIM_OBJECT_PARAMS(DTB) |
616 | 622 |
617 Param<int> size; | 623 BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) |
618 | 624 |
619END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) | 625 INIT_PARAM_DFLT(size, "TLB size", 64) |
620 | 626 |
621BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB) | 627 END_INIT_SIM_OBJECT_PARAMS(DTB) |
622 | 628 |
623 INIT_PARAM_DFLT(size, "TLB size", 64) | |
624 | 629 |
625END_INIT_SIM_OBJECT_PARAMS(AlphaDTB) | 630 CREATE_SIM_OBJECT(DTB) 631 { 632 return new DTB(getInstanceName(), size); 633 } |
626 | 634 |
627 628CREATE_SIM_OBJECT(AlphaDTB) 629{ 630 return new AlphaDTB(getInstanceName(), size); | 635 REGISTER_SIM_OBJECT("AlphaDTB", DTB) |
631} | 636} |
632 633REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB) 634 | |