tlb.cc (2665:a124942bacb8) tlb.cc (2680:246e7104f744)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#include <string>
34#include <vector>
35
36#include "arch/alpha/tlb.hh"
37#include "base/inifile.hh"
38#include "base/str.hh"
39#include "base/trace.hh"
40#include "config/alpha_tlaser.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#include <string>
34#include <vector>
35
36#include "arch/alpha/tlb.hh"
37#include "base/inifile.hh"
38#include "base/str.hh"
39#include "base/trace.hh"
40#include "config/alpha_tlaser.hh"
41#include "cpu/exec_context.hh"
41#include "cpu/thread_context.hh"
42#include "sim/builder.hh"
43
44using namespace std;
45using namespace EV5;
46
47///////////////////////////////////////////////////////////////////////
48//
49// Alpha TLB

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281 .name(name() + ".accesses")
282 .desc("ITB accesses");
283
284 accesses = hits + misses;
285}
286
287
288Fault
42#include "sim/builder.hh"
43
44using namespace std;
45using namespace EV5;
46
47///////////////////////////////////////////////////////////////////////
48//
49// Alpha TLB

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281 .name(name() + ".accesses")
282 .desc("ITB accesses");
283
284 accesses = hits + misses;
285}
286
287
288Fault
289AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
289AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const
290{
291 if (AlphaISA::PcPAL(req->getVaddr())) {
292 // strip off PAL PC marker (lsb is 1)
293 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
294 hits++;
295 return NoFault;
296 }
297

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303 acv++;
304 return new ItbAcvFault(req->getVaddr());
305 }
306
307
308 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
309 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
310#if ALPHA_TLASER
290{
291 if (AlphaISA::PcPAL(req->getVaddr())) {
292 // strip off PAL PC marker (lsb is 1)
293 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
294 hits++;
295 return NoFault;
296 }
297

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303 acv++;
304 return new ItbAcvFault(req->getVaddr());
305 }
306
307
308 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
309 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
310#if ALPHA_TLASER
311 if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
311 if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
312 VAddrSpaceEV5(req->getVaddr()) == 2) {
313#else
314 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
315#endif
316 // only valid in kernel mode
312 VAddrSpaceEV5(req->getVaddr()) == 2) {
313#else
314 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
315#endif
316 // only valid in kernel mode
317 if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
317 if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) !=
318 AlphaISA::mode_kernel) {
319 acv++;
320 return new ItbAcvFault(req->getVaddr());
321 }
322
323 req->setPaddr(req->getVaddr() & PAddrImplMask);
324
325#if !ALPHA_TLASER
326 // sign extend the physical address properly
327 if (req->getPaddr() & PAddrUncachedBit40)
328 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
329 else
330 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
331#endif
332
333 } else {
334 // not a physical address: need to look up pte
318 AlphaISA::mode_kernel) {
319 acv++;
320 return new ItbAcvFault(req->getVaddr());
321 }
322
323 req->setPaddr(req->getVaddr() & PAddrImplMask);
324
325#if !ALPHA_TLASER
326 // sign extend the physical address properly
327 if (req->getPaddr() & PAddrUncachedBit40)
328 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
329 else
330 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
331#endif
332
333 } else {
334 // not a physical address: need to look up pte
335 int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
335 int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
336 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
337 asn);
338
339 if (!pte) {
340 misses++;
341 return new ItbPageFault(req->getVaddr());
342 }
343
344 req->setPaddr((pte->ppn << AlphaISA::PageShift) +
345 (AlphaISA::VAddr(req->getVaddr()).offset()
346 & ~3));
347
348 // check permissions for this access
349 if (!(pte->xre &
336 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
337 asn);
338
339 if (!pte) {
340 misses++;
341 return new ItbPageFault(req->getVaddr());
342 }
343
344 req->setPaddr((pte->ppn << AlphaISA::PageShift) +
345 (AlphaISA::VAddr(req->getVaddr()).offset()
346 & ~3));
347
348 // check permissions for this access
349 if (!(pte->xre &
350 (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
350 (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) {
351 // instruction access fault
352 acv++;
353 return new ItbAcvFault(req->getVaddr());
354 }
355
356 hits++;
357 }
358 }

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438
439 hits = read_hits + write_hits;
440 misses = read_misses + write_misses;
441 acv = read_acv + write_acv;
442 accesses = read_accesses + write_accesses;
443}
444
445Fault
351 // instruction access fault
352 acv++;
353 return new ItbAcvFault(req->getVaddr());
354 }
355
356 hits++;
357 }
358 }

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438
439 hits = read_hits + write_hits;
440 misses = read_misses + write_misses;
441 acv = read_acv + write_acv;
442 accesses = read_accesses + write_accesses;
443}
444
445Fault
446AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
446AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
447{
447{
448 Addr pc = xc->readPC();
448 Addr pc = tc->readPC();
449
450 AlphaISA::mode_type mode =
449
450 AlphaISA::mode_type mode =
451 (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
451 (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM));
452
453
454 /**
455 * Check for alignment faults
456 */
457 if (req->getVaddr() & (req->getSize() - 1)) {
458 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
459 req->getSize());
460 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
461 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
462 }
463
464 if (pc & 0x1) {
465 mode = (req->getFlags() & ALTMODE) ?
466 (AlphaISA::mode_type)ALT_MODE_AM(
452
453
454 /**
455 * Check for alignment faults
456 */
457 if (req->getVaddr() & (req->getSize() - 1)) {
458 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
459 req->getSize());
460 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
461 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
462 }
463
464 if (pc & 0x1) {
465 mode = (req->getFlags() & ALTMODE) ?
466 (AlphaISA::mode_type)ALT_MODE_AM(
467 xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
467 tc->readMiscReg(AlphaISA::IPR_ALT_MODE))
468 : AlphaISA::mode_kernel;
469 }
470
471 if (req->getFlags() & PHYSICAL) {
472 req->setPaddr(req->getVaddr());
473 } else {
474 // verify that this is a good virtual address
475 if (!validVirtualAddress(req->getVaddr())) {
476 if (write) { write_acv++; } else { read_acv++; }
477 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
478 MM_STAT_BAD_VA_MASK |
479 MM_STAT_ACV_MASK;
480 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
481 }
482
483 // Check for "superpage" mapping
484#if ALPHA_TLASER
468 : AlphaISA::mode_kernel;
469 }
470
471 if (req->getFlags() & PHYSICAL) {
472 req->setPaddr(req->getVaddr());
473 } else {
474 // verify that this is a good virtual address
475 if (!validVirtualAddress(req->getVaddr())) {
476 if (write) { write_acv++; } else { read_acv++; }
477 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
478 MM_STAT_BAD_VA_MASK |
479 MM_STAT_ACV_MASK;
480 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
481 }
482
483 // Check for "superpage" mapping
484#if ALPHA_TLASER
485 if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
485 if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
486 VAddrSpaceEV5(req->getVaddr()) == 2) {
487#else
488 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
489#endif
490
491 // only valid in kernel mode
486 VAddrSpaceEV5(req->getVaddr()) == 2) {
487#else
488 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
489#endif
490
491 // only valid in kernel mode
492 if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
492 if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
493 AlphaISA::mode_kernel) {
494 if (write) { write_acv++; } else { read_acv++; }
495 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
496 MM_STAT_ACV_MASK);
497 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
498 }
499
500 req->setPaddr(req->getVaddr() & PAddrImplMask);

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508#endif
509
510 } else {
511 if (write)
512 write_accesses++;
513 else
514 read_accesses++;
515
493 AlphaISA::mode_kernel) {
494 if (write) { write_acv++; } else { read_acv++; }
495 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
496 MM_STAT_ACV_MASK);
497 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
498 }
499
500 req->setPaddr(req->getVaddr() & PAddrImplMask);

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508#endif
509
510 } else {
511 if (write)
512 write_accesses++;
513 else
514 read_accesses++;
515
516 int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
516 int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
517
518 // not a physical address: need to look up pte
519 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
520 asn);
521
522 if (!pte) {
523 // page fault
524 if (write) { write_misses++; } else { read_misses++; }

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518 // not a physical address: need to look up pte
519 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
520 asn);
521
522 if (!pte) {
523 // page fault
524 if (write) { write_misses++; } else { read_misses++; }

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