tlb.cc (12406:86bde4a026b5) | tlb.cc (12749:223c83ed9979) |
---|---|
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 189 unchanged lines hidden (view full) --- 198 } 199 200 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 201 retval ? "hit" : "miss", retval ? retval->ppn : 0); 202 return retval; 203} 204 205Fault | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 189 unchanged lines hidden (view full) --- 198 } 199 200 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 201 retval ? "hit" : "miss", retval ? retval->ppn : 0); 202 return retval; 203} 204 205Fault |
206TLB::checkCacheability(RequestPtr &req, bool itb) | 206TLB::checkCacheability(const RequestPtr &req, bool itb) |
207{ 208 // in Alpha, cacheability is controlled by upper-level bits of the 209 // physical address 210 211 /* 212 * We support having the uncacheable bit in either bit 39 or bit 213 * 40. The Turbolaser platform (and EV5) support having the bit 214 * in 39, but Tsunami (which Linux assumes uses an EV6) generates --- 152 unchanged lines hidden (view full) --- 367 table[i].unserializeSection(cp, csprintf("Entry%d", i)); 368 if (table[i].valid) { 369 lookupTable.insert(make_pair(table[i].tag, i)); 370 } 371 } 372} 373 374Fault | 207{ 208 // in Alpha, cacheability is controlled by upper-level bits of the 209 // physical address 210 211 /* 212 * We support having the uncacheable bit in either bit 39 or bit 213 * 40. The Turbolaser platform (and EV5) support having the bit 214 * in 39, but Tsunami (which Linux assumes uses an EV6) generates --- 152 unchanged lines hidden (view full) --- 367 table[i].unserializeSection(cp, csprintf("Entry%d", i)); 368 if (table[i].valid) { 369 lookupTable.insert(make_pair(table[i].tag, i)); 370 } 371 } 372} 373 374Fault |
375TLB::translateInst(RequestPtr req, ThreadContext *tc) | 375TLB::translateInst(const RequestPtr &req, ThreadContext *tc) |
376{ 377 //If this is a pal pc, then set PHYSICAL 378 if (FullSystem && PcPAL(req->getPC())) 379 req->setFlags(Request::PHYSICAL); 380 381 if (PcPAL(req->getPC())) { 382 // strip off PAL PC marker (lsb is 1) 383 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); --- 60 unchanged lines hidden (view full) --- 444 return std::make_shared<MachineCheckFault>(); 445 } 446 447 return checkCacheability(req, true); 448 449} 450 451Fault | 376{ 377 //If this is a pal pc, then set PHYSICAL 378 if (FullSystem && PcPAL(req->getPC())) 379 req->setFlags(Request::PHYSICAL); 380 381 if (PcPAL(req->getPC())) { 382 // strip off PAL PC marker (lsb is 1) 383 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); --- 60 unchanged lines hidden (view full) --- 444 return std::make_shared<MachineCheckFault>(); 445 } 446 447 return checkCacheability(req, true); 448 449} 450 451Fault |
452TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) | 452TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) |
453{ 454 mode_type mode = 455 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 456 457 /** 458 * Check for alignment faults 459 */ 460 if (req->getVaddr() & (req->getSize() - 1)) { --- 133 unchanged lines hidden (view full) --- 594 595 if (advance) 596 nextnlu(); 597 598 return *entry; 599} 600 601Fault | 453{ 454 mode_type mode = 455 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 456 457 /** 458 * Check for alignment faults 459 */ 460 if (req->getVaddr() & (req->getSize() - 1)) { --- 133 unchanged lines hidden (view full) --- 594 595 if (advance) 596 nextnlu(); 597 598 return *entry; 599} 600 601Fault |
602TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) | 602TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) |
603{ 604 if (mode == Execute) 605 return translateInst(req, tc); 606 else 607 return translateData(req, tc, mode == Write); 608} 609 610void | 603{ 604 if (mode == Execute) 605 return translateInst(req, tc); 606 else 607 return translateData(req, tc, mode == Write); 608} 609 610void |
611TLB::translateTiming(RequestPtr req, ThreadContext *tc, | 611TLB::translateTiming(const RequestPtr &req, ThreadContext *tc, |
612 Translation *translation, Mode mode) 613{ 614 assert(translation); 615 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 616} 617 618Fault | 612 Translation *translation, Mode mode) 613{ 614 assert(translation); 615 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 616} 617 618Fault |
619TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const | 619TLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc, 620 Mode mode) const |
620{ 621 return NoFault; 622} 623 624} // namespace AlphaISA 625 626AlphaISA::TLB * 627AlphaTLBParams::create() 628{ 629 return new AlphaISA::TLB(this); 630} | 621{ 622 return NoFault; 623} 624 625} // namespace AlphaISA 626 627AlphaISA::TLB * 628AlphaTLBParams::create() 629{ 630 return new AlphaISA::TLB(this); 631} |