1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Steve Reinhardt
30 * Andrew Schultz
31 */
32
33#include <string>
34#include <vector>
35
36#include "arch/alpha/pagetable.hh"
37#include "arch/alpha/tlb.hh"
38#include "arch/alpha/faults.hh"
39#include "base/inifile.hh"
40#include "base/str.hh"
41#include "base/trace.hh"
42#include "config/alpha_tlaser.hh"
43#include "cpu/thread_context.hh"
44#include "params/AlphaDTB.hh"
45#include "params/AlphaITB.hh"
44
45using namespace std;
46using namespace EV5;
47
48namespace AlphaISA {
49///////////////////////////////////////////////////////////////////////
50//
51// Alpha TLB
52//
53#ifdef DEBUG
54bool uncacheBit39 = false;
55bool uncacheBit40 = false;
56#endif
57
58#define MODE2MASK(X) (1 << (X))
59
62TLB::TLB(const string &name, int s)
63 : SimObject(name), size(s), nlu(0)
60TLB::TLB(const Params *p)
61 : SimObject(p), size(p->size), nlu(0)
62{
63 table = new TlbEntry[size];
64 memset(table, 0, sizeof(TlbEntry[size]));
65 flushCache();
66}
67
68TLB::~TLB()
69{
70 if (table)
71 delete [] table;
72}
73
74// look up an entry in the TLB
75TlbEntry *
76TLB::lookup(Addr vpn, uint8_t asn)
77{
78 // assume not found...
79 TlbEntry *retval = NULL;
80
81 if (EntryCache[0]) {
82 if (vpn == EntryCache[0]->tag &&
83 (EntryCache[0]->asma || EntryCache[0]->asn == asn))
84 retval = EntryCache[0];
85 else if (EntryCache[1]) {
86 if (vpn == EntryCache[1]->tag &&
87 (EntryCache[1]->asma || EntryCache[1]->asn == asn))
88 retval = EntryCache[1];
89 else if (EntryCache[2] && vpn == EntryCache[2]->tag &&
90 (EntryCache[2]->asma || EntryCache[2]->asn == asn))
91 retval = EntryCache[2];
92 }
93 }
94
95 if (retval == NULL) {
96 PageTable::const_iterator i = lookupTable.find(vpn);
97 if (i != lookupTable.end()) {
98 while (i->first == vpn) {
99 int index = i->second;
100 TlbEntry *entry = &table[index];
101 assert(entry->valid);
102 if (vpn == entry->tag && (entry->asma || entry->asn == asn)) {
103 retval = updateCache(entry);
104 break;
105 }
106
107 ++i;
108 }
109 }
110 }
111
112 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
113 retval ? "hit" : "miss", retval ? retval->ppn : 0);
114 return retval;
115}
116
117
118Fault
119TLB::checkCacheability(RequestPtr &req)
120{
121// in Alpha, cacheability is controlled by upper-level bits of the
122// physical address
123
124/*
125 * We support having the uncacheable bit in either bit 39 or bit 40.
126 * The Turbolaser platform (and EV5) support having the bit in 39, but
127 * Tsunami (which Linux assumes uses an EV6) generates accesses with
128 * the bit in 40. So we must check for both, but we have debug flags
129 * to catch a weird case where both are used, which shouldn't happen.
130 */
131
132
133#if ALPHA_TLASER
134 if (req->getPaddr() & PAddrUncachedBit39)
135#else
136 if (req->getPaddr() & PAddrUncachedBit43)
137#endif
138 {
139 // IPR memory space not implemented
140 if (PAddrIprSpace(req->getPaddr())) {
141 return new UnimpFault("IPR memory space not implemented!");
142 } else {
143 // mark request as uncacheable
144 req->setFlags(req->getFlags() | UNCACHEABLE);
145
146#if !ALPHA_TLASER
147 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
148 req->setPaddr(req->getPaddr() & PAddrUncachedMask);
149#endif
150 }
151 }
152 return NoFault;
153}
154
155
156// insert a new TLB entry
157void
158TLB::insert(Addr addr, TlbEntry &entry)
159{
160 flushCache();
161 VAddr vaddr = addr;
162 if (table[nlu].valid) {
163 Addr oldvpn = table[nlu].tag;
164 PageTable::iterator i = lookupTable.find(oldvpn);
165
166 if (i == lookupTable.end())
167 panic("TLB entry not found in lookupTable");
168
169 int index;
170 while ((index = i->second) != nlu) {
171 if (table[index].tag != oldvpn)
172 panic("TLB entry not found in lookupTable");
173
174 ++i;
175 }
176
177 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
178
179 lookupTable.erase(i);
180 }
181
182 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn);
183
184 table[nlu] = entry;
185 table[nlu].tag = vaddr.vpn();
186 table[nlu].valid = true;
187
188 lookupTable.insert(make_pair(vaddr.vpn(), nlu));
189 nextnlu();
190}
191
192void
193TLB::flushAll()
194{
195 DPRINTF(TLB, "flushAll\n");
196 memset(table, 0, sizeof(TlbEntry[size]));
197 flushCache();
198 lookupTable.clear();
199 nlu = 0;
200}
201
202void
203TLB::flushProcesses()
204{
205 flushCache();
206 PageTable::iterator i = lookupTable.begin();
207 PageTable::iterator end = lookupTable.end();
208 while (i != end) {
209 int index = i->second;
210 TlbEntry *entry = &table[index];
211 assert(entry->valid);
212
213 // we can't increment i after we erase it, so save a copy and
214 // increment it to get the next entry now
215 PageTable::iterator cur = i;
216 ++i;
217
218 if (!entry->asma) {
219 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, entry->tag, entry->ppn);
220 entry->valid = false;
221 lookupTable.erase(cur);
222 }
223 }
224}
225
226void
227TLB::flushAddr(Addr addr, uint8_t asn)
228{
229 flushCache();
230 VAddr vaddr = addr;
231
232 PageTable::iterator i = lookupTable.find(vaddr.vpn());
233 if (i == lookupTable.end())
234 return;
235
236 while (i != lookupTable.end() && i->first == vaddr.vpn()) {
237 int index = i->second;
238 TlbEntry *entry = &table[index];
239 assert(entry->valid);
240
241 if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) {
242 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
243 entry->ppn);
244
245 // invalidate this entry
246 entry->valid = false;
247
248 lookupTable.erase(i++);
249 } else {
250 ++i;
251 }
252 }
253}
254
255
256void
257TLB::serialize(ostream &os)
258{
259 SERIALIZE_SCALAR(size);
260 SERIALIZE_SCALAR(nlu);
261
262 for (int i = 0; i < size; i++) {
263 nameOut(os, csprintf("%s.Entry%d", name(), i));
264 table[i].serialize(os);
265 }
266}
267
268void
269TLB::unserialize(Checkpoint *cp, const string &section)
270{
271 UNSERIALIZE_SCALAR(size);
272 UNSERIALIZE_SCALAR(nlu);
273
274 for (int i = 0; i < size; i++) {
275 table[i].unserialize(cp, csprintf("%s.Entry%d", section, i));
276 if (table[i].valid) {
277 lookupTable.insert(make_pair(table[i].tag, i));
278 }
279 }
280}
281
282
283///////////////////////////////////////////////////////////////////////
284//
285// Alpha ITB
286//
289ITB::ITB(const std::string &name, int size)
290 : TLB(name, size)
287ITB::ITB(const Params *p)
288 : TLB(p)
289{}
290
291
292void
293ITB::regStats()
294{
295 hits
296 .name(name() + ".hits")
297 .desc("ITB hits");
298 misses
299 .name(name() + ".misses")
300 .desc("ITB misses");
301 acv
302 .name(name() + ".acv")
303 .desc("ITB acv");
304 accesses
305 .name(name() + ".accesses")
306 .desc("ITB accesses");
307
308 accesses = hits + misses;
309}
310
311
312Fault
313ITB::translate(RequestPtr &req, ThreadContext *tc)
314{
315 //If this is a pal pc, then set PHYSICAL
316 if(FULL_SYSTEM && PcPAL(req->getPC()))
317 req->setFlags(req->getFlags() | PHYSICAL);
318
319 if (PcPAL(req->getPC())) {
320 // strip off PAL PC marker (lsb is 1)
321 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
322 hits++;
323 return NoFault;
324 }
325
326 if (req->getFlags() & PHYSICAL) {
327 req->setPaddr(req->getVaddr());
328 } else {
329 // verify that this is a good virtual address
330 if (!validVirtualAddress(req->getVaddr())) {
331 acv++;
332 return new ItbAcvFault(req->getVaddr());
333 }
334
335
336 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
337 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
338#if ALPHA_TLASER
339 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
340 VAddrSpaceEV5(req->getVaddr()) == 2)
341#else
342 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
343#endif
344 {
345 // only valid in kernel mode
346 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
347 mode_kernel) {
348 acv++;
349 return new ItbAcvFault(req->getVaddr());
350 }
351
352 req->setPaddr(req->getVaddr() & PAddrImplMask);
353
354#if !ALPHA_TLASER
355 // sign extend the physical address properly
356 if (req->getPaddr() & PAddrUncachedBit40)
357 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
358 else
359 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
360#endif
361
362 } else {
363 // not a physical address: need to look up pte
364 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
365 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(),
366 asn);
367
368 if (!entry) {
369 misses++;
370 return new ItbPageFault(req->getVaddr());
371 }
372
373 req->setPaddr((entry->ppn << PageShift) +
374 (VAddr(req->getVaddr()).offset()
375 & ~3));
376
377 // check permissions for this access
378 if (!(entry->xre &
379 (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
380 // instruction access fault
381 acv++;
382 return new ItbAcvFault(req->getVaddr());
383 }
384
385 hits++;
386 }
387 }
388
389 // check that the physical address is ok (catch bad physical addresses)
390 if (req->getPaddr() & ~PAddrImplMask)
391 return genMachineCheckFault();
392
393 return checkCacheability(req);
394
395}
396
397///////////////////////////////////////////////////////////////////////
398//
399// Alpha DTB
400//
403 DTB::DTB(const std::string &name, int size)
404 : TLB(name, size)
401 DTB::DTB(const Params *p)
402 : TLB(p)
403{}
404
405void
406DTB::regStats()
407{
408 read_hits
409 .name(name() + ".read_hits")
410 .desc("DTB read hits")
411 ;
412
413 read_misses
414 .name(name() + ".read_misses")
415 .desc("DTB read misses")
416 ;
417
418 read_acv
419 .name(name() + ".read_acv")
420 .desc("DTB read access violations")
421 ;
422
423 read_accesses
424 .name(name() + ".read_accesses")
425 .desc("DTB read accesses")
426 ;
427
428 write_hits
429 .name(name() + ".write_hits")
430 .desc("DTB write hits")
431 ;
432
433 write_misses
434 .name(name() + ".write_misses")
435 .desc("DTB write misses")
436 ;
437
438 write_acv
439 .name(name() + ".write_acv")
440 .desc("DTB write access violations")
441 ;
442
443 write_accesses
444 .name(name() + ".write_accesses")
445 .desc("DTB write accesses")
446 ;
447
448 hits
449 .name(name() + ".hits")
450 .desc("DTB hits")
451 ;
452
453 misses
454 .name(name() + ".misses")
455 .desc("DTB misses")
456 ;
457
458 acv
459 .name(name() + ".acv")
460 .desc("DTB access violations")
461 ;
462
463 accesses
464 .name(name() + ".accesses")
465 .desc("DTB accesses")
466 ;
467
468 hits = read_hits + write_hits;
469 misses = read_misses + write_misses;
470 acv = read_acv + write_acv;
471 accesses = read_accesses + write_accesses;
472}
473
474Fault
475DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
476{
477 Addr pc = tc->readPC();
478
479 mode_type mode =
480 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
481
482
483 /**
484 * Check for alignment faults
485 */
486 if (req->getVaddr() & (req->getSize() - 1)) {
487 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
488 req->getSize());
489 uint64_t flags = write ? MM_STAT_WR_MASK : 0;
490 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
491 }
492
493 if (PcPAL(pc)) {
494 mode = (req->getFlags() & ALTMODE) ?
495 (mode_type)ALT_MODE_AM(
496 tc->readMiscRegNoEffect(IPR_ALT_MODE))
497 : mode_kernel;
498 }
499
500 if (req->getFlags() & PHYSICAL) {
501 req->setPaddr(req->getVaddr());
502 } else {
503 // verify that this is a good virtual address
504 if (!validVirtualAddress(req->getVaddr())) {
505 if (write) { write_acv++; } else { read_acv++; }
506 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
507 MM_STAT_BAD_VA_MASK |
508 MM_STAT_ACV_MASK;
509 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
510 }
511
512 // Check for "superpage" mapping
513#if ALPHA_TLASER
514 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
515 VAddrSpaceEV5(req->getVaddr()) == 2)
516#else
517 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
518#endif
519 {
520
521 // only valid in kernel mode
522 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
523 mode_kernel) {
524 if (write) { write_acv++; } else { read_acv++; }
525 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
526 MM_STAT_ACV_MASK);
527 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
528 }
529
530 req->setPaddr(req->getVaddr() & PAddrImplMask);
531
532#if !ALPHA_TLASER
533 // sign extend the physical address properly
534 if (req->getPaddr() & PAddrUncachedBit40)
535 req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
536 else
537 req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
538#endif
539
540 } else {
541 if (write)
542 write_accesses++;
543 else
544 read_accesses++;
545
546 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
547
548 // not a physical address: need to look up pte
549 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn);
550
551 if (!entry) {
552 // page fault
553 if (write) { write_misses++; } else { read_misses++; }
554 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
555 MM_STAT_DTB_MISS_MASK;
556 return (req->getFlags() & VPTE) ?
557 (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
558 flags)) :
559 (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
560 flags));
561 }
562
563 req->setPaddr((entry->ppn << PageShift) +
564 VAddr(req->getVaddr()).offset());
565
566 if (write) {
567 if (!(entry->xwe & MODE2MASK(mode))) {
568 // declare the instruction access fault
569 write_acv++;
570 uint64_t flags = MM_STAT_WR_MASK |
571 MM_STAT_ACV_MASK |
572 (entry->fonw ? MM_STAT_FONW_MASK : 0);
573 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
574 }
575 if (entry->fonw) {
576 write_acv++;
577 uint64_t flags = MM_STAT_WR_MASK |
578 MM_STAT_FONW_MASK;
579 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
580 }
581 } else {
582 if (!(entry->xre & MODE2MASK(mode))) {
583 read_acv++;
584 uint64_t flags = MM_STAT_ACV_MASK |
585 (entry->fonr ? MM_STAT_FONR_MASK : 0);
586 return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
587 }
588 if (entry->fonr) {
589 read_acv++;
590 uint64_t flags = MM_STAT_FONR_MASK;
591 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
592 }
593 }
594 }
595
596 if (write)
597 write_hits++;
598 else
599 read_hits++;
600 }
601
602 // check that the physical address is ok (catch bad physical addresses)
603 if (req->getPaddr() & ~PAddrImplMask)
604 return genMachineCheckFault();
605
606 return checkCacheability(req);
607}
608
609TlbEntry &
610TLB::index(bool advance)
611{
612 TlbEntry *entry = &table[nlu];
613
614 if (advance)
615 nextnlu();
616
617 return *entry;
618}
619
620/* end namespace AlphaISA */ }
621
622AlphaISA::ITB *
623AlphaITBParams::create()
624{
627 return new AlphaISA::ITB(name, size);
625 return new AlphaISA::ITB(this);
626}
627
628AlphaISA::DTB *
629AlphaDTBParams::create()
630{
633 return new AlphaISA::DTB(name, size);
631 return new AlphaISA::DTB(this);
632}