1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31 */ 32 33#include <string> 34#include <vector> 35 36#include "arch/alpha/faults.hh" 37#include "arch/alpha/pagetable.hh" 38#include "arch/alpha/tlb.hh" |
39#include "arch/generic/debugfaults.hh" |
40#include "base/inifile.hh" 41#include "base/str.hh" 42#include "base/trace.hh" 43#include "cpu/thread_context.hh" 44#include "debug/TLB.hh" 45 46using namespace std; 47 --- 382 unchanged lines hidden (view full) --- 430 return new ItbAcvFault(req->getVaddr()); 431 } 432 433 fetch_hits++; 434 } 435 } 436 437 // check that the physical address is ok (catch bad physical addresses) |
438 if (req->getPaddr() & ~PAddrImplMask) { 439 return new MachineCheckFault(); 440 } |
441 442 return checkCacheability(req, true); 443 444} 445 446Fault 447TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 448{ --- 110 unchanged lines hidden (view full) --- 559 560 if (write) 561 write_hits++; 562 else 563 read_hits++; 564 } 565 566 // check that the physical address is ok (catch bad physical addresses) |
567 if (req->getPaddr() & ~PAddrImplMask) { 568 return new MachineCheckFault(); 569 } |
570 571 return checkCacheability(req); 572} 573 574TlbEntry & 575TLB::index(bool advance) 576{ 577 TlbEntry *entry = &table[nlu]; --- 31 unchanged lines hidden --- |