1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34#include <vector> 35 36#include "arch/alpha/pagetable.hh" 37#include "arch/alpha/tlb.hh" 38#include "arch/alpha/faults.hh" 39#include "base/inifile.hh" 40#include "base/str.hh" 41#include "base/trace.hh" |
42#include "cpu/thread_context.hh" 43 44using namespace std; 45 46namespace AlphaISA { 47 48/////////////////////////////////////////////////////////////////////// 49// --- 159 unchanged lines hidden (view full) --- 209 * 40. The Turbolaser platform (and EV5) support having the bit 210 * in 39, but Tsunami (which Linux assumes uses an EV6) generates 211 * accesses with the bit in 40. So we must check for both, but we 212 * have debug flags to catch a weird case where both are used, 213 * which shouldn't happen. 214 */ 215 216 |
217 if (req->getPaddr() & PAddrUncachedBit43) { |
218 // IPR memory space not implemented 219 if (PAddrIprSpace(req->getPaddr())) { 220 return new UnimpFault("IPR memory space not implemented!"); 221 } else { 222 // mark request as uncacheable 223 req->setFlags(Request::UNCACHEABLE); 224 |
225 // Clear bits 42:35 of the physical address (10-2 in 226 // Tsunami manual) 227 req->setPaddr(req->getPaddr() & PAddrUncachedMask); |
228 } 229 // We shouldn't be able to read from an uncachable address in Alpha as 230 // we don't have a ROM and we don't want to try to fetch from a device 231 // register as we destroy any data that is clear-on-read. 232 if (req->isUncacheable() && itb) 233 return new UnimpFault("CPU trying to fetch from uncached I/O"); 234 235 } --- 149 unchanged lines hidden (view full) --- 385 if (!validVirtualAddress(req->getVaddr())) { 386 fetch_acv++; 387 return new ItbAcvFault(req->getVaddr()); 388 } 389 390 391 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 392 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 |
393 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { |
394 // only valid in kernel mode 395 if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 396 mode_kernel) { 397 fetch_acv++; 398 return new ItbAcvFault(req->getVaddr()); 399 } 400 401 req->setPaddr(req->getVaddr() & PAddrImplMask); 402 |
403 // sign extend the physical address properly 404 if (req->getPaddr() & PAddrUncachedBit40) 405 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 406 else 407 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); |
408 } else { 409 // not a physical address: need to look up pte 410 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 411 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 412 asn); 413 414 if (!entry) { 415 fetch_misses++; --- 57 unchanged lines hidden (view full) --- 473 if (write) { write_acv++; } else { read_acv++; } 474 uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 475 MM_STAT_BAD_VA_MASK | 476 MM_STAT_ACV_MASK; 477 return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 478 } 479 480 // Check for "superpage" mapping |
481 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { |
482 // only valid in kernel mode 483 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 484 mode_kernel) { 485 if (write) { write_acv++; } else { read_acv++; } 486 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 487 MM_STAT_ACV_MASK); 488 489 return new DtbAcvFault(req->getVaddr(), req->getFlags(), 490 flags); 491 } 492 493 req->setPaddr(req->getVaddr() & PAddrImplMask); 494 |
495 // sign extend the physical address properly 496 if (req->getPaddr() & PAddrUncachedBit40) 497 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 498 else 499 req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); |
500 } else { 501 if (write) 502 write_accesses++; 503 else 504 read_accesses++; 505 506 int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 507 --- 99 unchanged lines hidden --- |