1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 31 unchanged lines hidden (view full) --- 40#include "base/str.hh" 41#include "base/trace.hh" 42#include "config/alpha_tlaser.hh" 43#include "cpu/thread_context.hh" 44 45using namespace std; 46 47namespace AlphaISA { |
48 |
49/////////////////////////////////////////////////////////////////////// 50// 51// Alpha TLB 52// |
53 |
54#ifdef DEBUG 55bool uncacheBit39 = false; 56bool uncacheBit40 = false; 57#endif 58 |
59#define MODE2MASK(X) (1 << (X)) |
60 61TLB::TLB(const Params *p) 62 : BaseTLB(p), size(p->size), nlu(0) 63{ 64 table = new TlbEntry[size]; 65 memset(table, 0, sizeof(TlbEntry[size])); 66 flushCache(); 67} --- 42 unchanged lines hidden (view full) --- 110 } 111 } 112 113 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 114 retval ? "hit" : "miss", retval ? retval->ppn : 0); 115 return retval; 116} 117 |
118Fault 119TLB::checkCacheability(RequestPtr &req, bool itb) 120{ |
121 // in Alpha, cacheability is controlled by upper-level bits of the 122 // physical address |
123 |
124 /* 125 * We support having the uncacheable bit in either bit 39 or bit 126 * 40. The Turbolaser platform (and EV5) support having the bit 127 * in 39, but Tsunami (which Linux assumes uses an EV6) generates 128 * accesses with the bit in 40. So we must check for both, but we 129 * have debug flags to catch a weird case where both are used, 130 * which shouldn't happen. 131 */ |
132 133 134#if ALPHA_TLASER 135 if (req->getPaddr() & PAddrUncachedBit39) 136#else 137 if (req->getPaddr() & PAddrUncachedBit43) 138#endif 139 { 140 // IPR memory space not implemented 141 if (PAddrIprSpace(req->getPaddr())) { 142 return new UnimpFault("IPR memory space not implemented!"); 143 } else { 144 // mark request as uncacheable 145 req->setFlags(req->getFlags() | UNCACHEABLE); 146 147#if !ALPHA_TLASER |
148 // Clear bits 42:35 of the physical address (10-2 in 149 // Tsunami manual) |
150 req->setPaddr(req->getPaddr() & PAddrUncachedMask); 151#endif 152 } 153 // We shouldn't be able to read from an uncachable address in Alpha as 154 // we don't have a ROM and we don't want to try to fetch from a device 155 // register as we destroy any data that is clear-on-read. 156 if (req->isUncacheable() && itb) 157 return new UnimpFault("CPU trying to fetch from uncached I/O"); --- 61 unchanged lines hidden (view full) --- 219 assert(entry->valid); 220 221 // we can't increment i after we erase it, so save a copy and 222 // increment it to get the next entry now 223 PageTable::iterator cur = i; 224 ++i; 225 226 if (!entry->asma) { |
227 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, 228 entry->tag, entry->ppn); |
229 entry->valid = false; 230 lookupTable.erase(cur); 231 } 232 } 233} 234 235void 236TLB::flushAddr(Addr addr, uint8_t asn) --- 46 unchanged lines hidden (view full) --- 283 for (int i = 0; i < size; i++) { 284 table[i].unserialize(cp, csprintf("%s.Entry%d", section, i)); 285 if (table[i].valid) { 286 lookupTable.insert(make_pair(table[i].tag, i)); 287 } 288 } 289} 290 |
291/////////////////////////////////////////////////////////////////////// 292// 293// Alpha ITB 294// 295ITB::ITB(const Params *p) 296 : TLB(p) 297{} 298 --- 12 unchanged lines hidden (view full) --- 311 .desc("ITB acv"); 312 accesses 313 .name(name() + ".accesses") 314 .desc("ITB accesses"); 315 316 accesses = hits + misses; 317} 318 |
319Fault 320ITB::translate(RequestPtr &req, ThreadContext *tc) 321{ 322 //If this is a pal pc, then set PHYSICAL |
323 if (FULL_SYSTEM && PcPAL(req->getPC())) |
324 req->setFlags(req->getFlags() | PHYSICAL); 325 326 if (PcPAL(req->getPC())) { 327 // strip off PAL PC marker (lsb is 1) 328 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 329 hits++; 330 return NoFault; 331 } --- 68 unchanged lines hidden (view full) --- 400 return checkCacheability(req, true); 401 402} 403 404/////////////////////////////////////////////////////////////////////// 405// 406// Alpha DTB 407// |
408DTB::DTB(const Params *p) |
409 : TLB(p) 410{} 411 412void 413DTB::regStats() 414{ 415 read_hits 416 .name(name() + ".read_hits") --- 64 unchanged lines hidden (view full) --- 481Fault 482DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 483{ 484 Addr pc = tc->readPC(); 485 486 mode_type mode = 487 (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 488 |
489 /** 490 * Check for alignment faults 491 */ 492 if (req->getVaddr() & (req->getSize() - 1)) { 493 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 494 req->getSize()); 495 uint64_t flags = write ? MM_STAT_WR_MASK : 0; 496 return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); --- 21 unchanged lines hidden (view full) --- 518 // Check for "superpage" mapping 519#if ALPHA_TLASER 520 if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 521 VAddrSpaceEV5(req->getVaddr()) == 2) 522#else 523 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 524#endif 525 { |
526 // only valid in kernel mode 527 if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 528 mode_kernel) { 529 if (write) { write_acv++; } else { read_acv++; } 530 uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 531 MM_STAT_ACV_MASK); |
532 533 return new DtbAcvFault(req->getVaddr(), req->getFlags(), 534 flags); |
535 } 536 537 req->setPaddr(req->getVaddr() & PAddrImplMask); 538 539#if !ALPHA_TLASER 540 // sign extend the physical address properly 541 if (req->getPaddr() & PAddrUncachedBit40) 542 req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); --- 29 unchanged lines hidden (view full) --- 572 573 if (write) { 574 if (!(entry->xwe & MODE2MASK(mode))) { 575 // declare the instruction access fault 576 write_acv++; 577 uint64_t flags = MM_STAT_WR_MASK | 578 MM_STAT_ACV_MASK | 579 (entry->fonw ? MM_STAT_FONW_MASK : 0); |
580 return new DtbPageFault(req->getVaddr(), req->getFlags(), 581 flags); |
582 } 583 if (entry->fonw) { 584 write_acv++; |
585 uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK; 586 return new DtbPageFault(req->getVaddr(), req->getFlags(), 587 flags); |
588 } 589 } else { 590 if (!(entry->xre & MODE2MASK(mode))) { 591 read_acv++; 592 uint64_t flags = MM_STAT_ACV_MASK | 593 (entry->fonr ? MM_STAT_FONR_MASK : 0); |
594 return new DtbAcvFault(req->getVaddr(), req->getFlags(), 595 flags); |
596 } 597 if (entry->fonr) { 598 read_acv++; 599 uint64_t flags = MM_STAT_FONR_MASK; |
600 return new DtbPageFault(req->getVaddr(), req->getFlags(), 601 flags); |
602 } 603 } 604 } 605 606 if (write) 607 write_hits++; 608 else 609 read_hits++; --- 12 unchanged lines hidden (view full) --- 622 TlbEntry *entry = &table[nlu]; 623 624 if (advance) 625 nextnlu(); 626 627 return *entry; 628} 629 |
630/* end namespace AlphaISA */ } |
631 632AlphaISA::ITB * 633AlphaITBParams::create() 634{ 635 return new AlphaISA::ITB(this); 636} 637 638AlphaISA::DTB * 639AlphaDTBParams::create() 640{ 641 return new AlphaISA::DTB(this); 642} |