47a48
>
51a53
>
57c59
< #define MODE2MASK(X) (1 << (X))
---
> #define MODE2MASK(X) (1 << (X))
116d117
<
120,121c121,122
< // in Alpha, cacheability is controlled by upper-level bits of the
< // physical address
---
> // in Alpha, cacheability is controlled by upper-level bits of the
> // physical address
123,129c124,131
< /*
< * We support having the uncacheable bit in either bit 39 or bit 40.
< * The Turbolaser platform (and EV5) support having the bit in 39, but
< * Tsunami (which Linux assumes uses an EV6) generates accesses with
< * the bit in 40. So we must check for both, but we have debug flags
< * to catch a weird case where both are used, which shouldn't happen.
< */
---
> /*
> * We support having the uncacheable bit in either bit 39 or bit
> * 40. The Turbolaser platform (and EV5) support having the bit
> * in 39, but Tsunami (which Linux assumes uses an EV6) generates
> * accesses with the bit in 40. So we must check for both, but we
> * have debug flags to catch a weird case where both are used,
> * which shouldn't happen.
> */
146c148,149
< // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
---
> // Clear bits 42:35 of the physical address (10-2 in
> // Tsunami manual)
224c227,228
< DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, entry->tag, entry->ppn);
---
> DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index,
> entry->tag, entry->ppn);
287d290
<
316d318
<
321c323
< if(FULL_SYSTEM && PcPAL(req->getPC()))
---
> if (FULL_SYSTEM && PcPAL(req->getPC()))
406c408
< DTB::DTB(const Params *p)
---
> DTB::DTB(const Params *p)
487d488
<
525d525
<
532c532,534
< return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
---
>
> return new DtbAcvFault(req->getVaddr(), req->getFlags(),
> flags);
578c580,581
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
---
> return new DtbPageFault(req->getVaddr(), req->getFlags(),
> flags);
582,584c585,587
< uint64_t flags = MM_STAT_WR_MASK |
< MM_STAT_FONW_MASK;
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
---
> uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK;
> return new DtbPageFault(req->getVaddr(), req->getFlags(),
> flags);
591c594,595
< return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
---
> return new DtbAcvFault(req->getVaddr(), req->getFlags(),
> flags);
596c600,601
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
---
> return new DtbPageFault(req->getVaddr(), req->getFlags(),
> flags);
625c630
< } // namespace AlphaISA
---
> /* end namespace AlphaISA */ }