49,52c49,54
< ///////////////////////////////////////////////////////////////////////
< //
< // Alpha TLB
< //
---
> namespace AlphaISA
> {
> ///////////////////////////////////////////////////////////////////////
> //
> // Alpha TLB
> //
54,55c56,57
< bool uncacheBit39 = false;
< bool uncacheBit40 = false;
---
> bool uncacheBit39 = false;
> bool uncacheBit40 = false;
60,65c62,67
< AlphaTLB::AlphaTLB(const string &name, int s)
< : SimObject(name), size(s), nlu(0)
< {
< table = new AlphaISA::PTE[size];
< memset(table, 0, sizeof(AlphaISA::PTE[size]));
< }
---
> TLB::TLB(const string &name, int s)
> : SimObject(name), size(s), nlu(0)
> {
> table = new PTE[size];
> memset(table, 0, sizeof(PTE[size]));
> }
67,71c69,73
< AlphaTLB::~AlphaTLB()
< {
< if (table)
< delete [] table;
< }
---
> TLB::~TLB()
> {
> if (table)
> delete [] table;
> }
73,78c75,80
< // look up an entry in the TLB
< AlphaISA::PTE *
< AlphaTLB::lookup(Addr vpn, uint8_t asn) const
< {
< // assume not found...
< AlphaISA::PTE *retval = NULL;
---
> // look up an entry in the TLB
> PTE *
> TLB::lookup(Addr vpn, uint8_t asn) const
> {
> // assume not found...
> PTE *retval = NULL;
80,89c82,91
< PageTable::const_iterator i = lookupTable.find(vpn);
< if (i != lookupTable.end()) {
< while (i->first == vpn) {
< int index = i->second;
< AlphaISA::PTE *pte = &table[index];
< assert(pte->valid);
< if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
< retval = pte;
< break;
< }
---
> PageTable::const_iterator i = lookupTable.find(vpn);
> if (i != lookupTable.end()) {
> while (i->first == vpn) {
> int index = i->second;
> PTE *pte = &table[index];
> assert(pte->valid);
> if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
> retval = pte;
> break;
> }
91c93,94
< ++i;
---
> ++i;
> }
92a96,99
>
> DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
> retval ? "hit" : "miss", retval ? retval->ppn : 0);
> return retval;
95,98d101
< DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
< retval ? "hit" : "miss", retval ? retval->ppn : 0);
< return retval;
< }
99a103,107
> Fault
> TLB::checkCacheability(RequestPtr &req)
> {
> // in Alpha, cacheability is controlled by upper-level bits of the
> // physical address
101,105c109,115
< Fault
< AlphaTLB::checkCacheability(RequestPtr &req)
< {
< // in Alpha, cacheability is controlled by upper-level bits of the
< // physical address
---
> /*
> * We support having the uncacheable bit in either bit 39 or bit 40.
> * The Turbolaser platform (and EV5) support having the bit in 39, but
> * Tsunami (which Linux assumes uses an EV6) generates accesses with
> * the bit in 40. So we must check for both, but we have debug flags
> * to catch a weird case where both are used, which shouldn't happen.
> */
107,113d116
< /*
< * We support having the uncacheable bit in either bit 39 or bit 40.
< * The Turbolaser platform (and EV5) support having the bit in 39, but
< * Tsunami (which Linux assumes uses an EV6) generates accesses with
< * the bit in 40. So we must check for both, but we have debug flags
< * to catch a weird case where both are used, which shouldn't happen.
< */
115d117
<
117c119
< if (req->getPaddr() & PAddrUncachedBit39) {
---
> if (req->getPaddr() & PAddrUncachedBit39) {
119c121
< if (req->getPaddr() & PAddrUncachedBit43) {
---
> if (req->getPaddr() & PAddrUncachedBit43) {
121,126c123,128
< // IPR memory space not implemented
< if (PAddrIprSpace(req->getPaddr())) {
< return new UnimpFault("IPR memory space not implemented!");
< } else {
< // mark request as uncacheable
< req->setFlags(req->getFlags() | UNCACHEABLE);
---
> // IPR memory space not implemented
> if (PAddrIprSpace(req->getPaddr())) {
> return new UnimpFault("IPR memory space not implemented!");
> } else {
> // mark request as uncacheable
> req->setFlags(req->getFlags() | UNCACHEABLE);
129,130c131,132
< // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
< req->setPaddr(req->getPaddr() & PAddrUncachedMask);
---
> // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
> req->setPaddr(req->getPaddr() & PAddrUncachedMask);
131a134
> }
132a136
> return NoFault;
134,135d137
< return NoFault;
< }
138,145c140,147
< // insert a new TLB entry
< void
< AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte)
< {
< AlphaISA::VAddr vaddr = addr;
< if (table[nlu].valid) {
< Addr oldvpn = table[nlu].tag;
< PageTable::iterator i = lookupTable.find(oldvpn);
---
> // insert a new TLB entry
> void
> TLB::insert(Addr addr, PTE &pte)
> {
> VAddr vaddr = addr;
> if (table[nlu].valid) {
> Addr oldvpn = table[nlu].tag;
> PageTable::iterator i = lookupTable.find(oldvpn);
147,152c149
< if (i == lookupTable.end())
< panic("TLB entry not found in lookupTable");
<
< int index;
< while ((index = i->second) != nlu) {
< if (table[index].tag != oldvpn)
---
> if (i == lookupTable.end())
155,156c152,155
< ++i;
< }
---
> int index;
> while ((index = i->second) != nlu) {
> if (table[index].tag != oldvpn)
> panic("TLB entry not found in lookupTable");
158c157,158
< DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
---
> ++i;
> }
160,161c160
< lookupTable.erase(i);
< }
---
> DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
163c162,163
< DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
---
> lookupTable.erase(i);
> }
165,167c165
< table[nlu] = pte;
< table[nlu].tag = vaddr.vpn();
< table[nlu].valid = true;
---
> DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
169,171c167,169
< lookupTable.insert(make_pair(vaddr.vpn(), nlu));
< nextnlu();
< }
---
> table[nlu] = pte;
> table[nlu].tag = vaddr.vpn();
> table[nlu].valid = true;
173,180c171,173
< void
< AlphaTLB::flushAll()
< {
< DPRINTF(TLB, "flushAll\n");
< memset(table, 0, sizeof(AlphaISA::PTE[size]));
< lookupTable.clear();
< nlu = 0;
< }
---
> lookupTable.insert(make_pair(vaddr.vpn(), nlu));
> nextnlu();
> }
182,190c175,182
< void
< AlphaTLB::flushProcesses()
< {
< PageTable::iterator i = lookupTable.begin();
< PageTable::iterator end = lookupTable.end();
< while (i != end) {
< int index = i->second;
< AlphaISA::PTE *pte = &table[index];
< assert(pte->valid);
---
> void
> TLB::flushAll()
> {
> DPRINTF(TLB, "flushAll\n");
> memset(table, 0, sizeof(PTE[size]));
> lookupTable.clear();
> nlu = 0;
> }
192,195c184,192
< // we can't increment i after we erase it, so save a copy and
< // increment it to get the next entry now
< PageTable::iterator cur = i;
< ++i;
---
> void
> TLB::flushProcesses()
> {
> PageTable::iterator i = lookupTable.begin();
> PageTable::iterator end = lookupTable.end();
> while (i != end) {
> int index = i->second;
> PTE *pte = &table[index];
> assert(pte->valid);
197,200c194,203
< if (!pte->asma) {
< DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
< pte->valid = false;
< lookupTable.erase(cur);
---
> // we can't increment i after we erase it, so save a copy and
> // increment it to get the next entry now
> PageTable::iterator cur = i;
> ++i;
>
> if (!pte->asma) {
> DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
> pte->valid = false;
> lookupTable.erase(cur);
> }
203d205
< }
205,208c207,210
< void
< AlphaTLB::flushAddr(Addr addr, uint8_t asn)
< {
< AlphaISA::VAddr vaddr = addr;
---
> void
> TLB::flushAddr(Addr addr, uint8_t asn)
> {
> VAddr vaddr = addr;
210,212c212,214
< PageTable::iterator i = lookupTable.find(vaddr.vpn());
< if (i == lookupTable.end())
< return;
---
> PageTable::iterator i = lookupTable.find(vaddr.vpn());
> if (i == lookupTable.end())
> return;
214,217c216,219
< while (i->first == vaddr.vpn()) {
< int index = i->second;
< AlphaISA::PTE *pte = &table[index];
< assert(pte->valid);
---
> while (i->first == vaddr.vpn()) {
> int index = i->second;
> PTE *pte = &table[index];
> assert(pte->valid);
219,221c221,223
< if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
< DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
< pte->ppn);
---
> if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
> DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
> pte->ppn);
223,224c225,226
< // invalidate this entry
< pte->valid = false;
---
> // invalidate this entry
> pte->valid = false;
226,227c228,229
< lookupTable.erase(i);
< }
---
> lookupTable.erase(i);
> }
229c231,232
< ++i;
---
> ++i;
> }
231d233
< }
234,238c236,240
< void
< AlphaTLB::serialize(ostream &os)
< {
< SERIALIZE_SCALAR(size);
< SERIALIZE_SCALAR(nlu);
---
> void
> TLB::serialize(ostream &os)
> {
> SERIALIZE_SCALAR(size);
> SERIALIZE_SCALAR(nlu);
240,242c242,245
< for (int i = 0; i < size; i++) {
< nameOut(os, csprintf("%s.PTE%d", name(), i));
< table[i].serialize(os);
---
> for (int i = 0; i < size; i++) {
> nameOut(os, csprintf("%s.PTE%d", name(), i));
> table[i].serialize(os);
> }
244d246
< }
246,250c248,252
< void
< AlphaTLB::unserialize(Checkpoint *cp, const string §ion)
< {
< UNSERIALIZE_SCALAR(size);
< UNSERIALIZE_SCALAR(nlu);
---
> void
> TLB::unserialize(Checkpoint *cp, const string §ion)
> {
> UNSERIALIZE_SCALAR(size);
> UNSERIALIZE_SCALAR(nlu);
252,255c254,258
< for (int i = 0; i < size; i++) {
< table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
< if (table[i].valid) {
< lookupTable.insert(make_pair(table[i].tag, i));
---
> for (int i = 0; i < size; i++) {
> table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
> if (table[i].valid) {
> lookupTable.insert(make_pair(table[i].tag, i));
> }
258d260
< }
261,267c263,269
< ///////////////////////////////////////////////////////////////////////
< //
< // Alpha ITB
< //
< AlphaITB::AlphaITB(const std::string &name, int size)
< : AlphaTLB(name, size)
< {}
---
> ///////////////////////////////////////////////////////////////////////
> //
> // Alpha ITB
> //
> ITB::ITB(const std::string &name, int size)
> : TLB(name, size)
> {}
270,284c272,286
< void
< AlphaITB::regStats()
< {
< hits
< .name(name() + ".hits")
< .desc("ITB hits");
< misses
< .name(name() + ".misses")
< .desc("ITB misses");
< acv
< .name(name() + ".acv")
< .desc("ITB acv");
< accesses
< .name(name() + ".accesses")
< .desc("ITB accesses");
---
> void
> ITB::regStats()
> {
> hits
> .name(name() + ".hits")
> .desc("ITB hits");
> misses
> .name(name() + ".misses")
> .desc("ITB misses");
> acv
> .name(name() + ".acv")
> .desc("ITB acv");
> accesses
> .name(name() + ".accesses")
> .desc("ITB accesses");
286,297c288
< accesses = hits + misses;
< }
<
<
< Fault
< AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const
< {
< if (AlphaISA::PcPAL(req->getVaddr())) {
< // strip off PAL PC marker (lsb is 1)
< req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
< hits++;
< return NoFault;
---
> accesses = hits + misses;
300,306c291,299
< if (req->getFlags() & PHYSICAL) {
< req->setPaddr(req->getVaddr());
< } else {
< // verify that this is a good virtual address
< if (!validVirtualAddress(req->getVaddr())) {
< acv++;
< return new ItbAcvFault(req->getVaddr());
---
>
> Fault
> ITB::translate(RequestPtr &req, ThreadContext *tc) const
> {
> if (PcPAL(req->getVaddr())) {
> // strip off PAL PC marker (lsb is 1)
> req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
> hits++;
> return NoFault;
308a302,309
> if (req->getFlags() & PHYSICAL) {
> req->setPaddr(req->getVaddr());
> } else {
> // verify that this is a good virtual address
> if (!validVirtualAddress(req->getVaddr())) {
> acv++;
> return new ItbAcvFault(req->getVaddr());
> }
310,311c311,313
< // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
< // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
---
>
> // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
> // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
313,314c315,316
< if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
< VAddrSpaceEV5(req->getVaddr()) == 2) {
---
> if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
> VAddrSpaceEV5(req->getVaddr()) == 2) {
316c318
< if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
---
> if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
318,323c320,325
< // only valid in kernel mode
< if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) !=
< AlphaISA::mode_kernel) {
< acv++;
< return new ItbAcvFault(req->getVaddr());
< }
---
> // only valid in kernel mode
> if (ICM_CM(tc->readMiscReg(IPR_ICM)) !=
> mode_kernel) {
> acv++;
> return new ItbAcvFault(req->getVaddr());
> }
325c327
< req->setPaddr(req->getVaddr() & PAddrImplMask);
---
> req->setPaddr(req->getVaddr() & PAddrImplMask);
328,332c330,334
< // sign extend the physical address properly
< if (req->getPaddr() & PAddrUncachedBit40)
< req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
< else
< req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
---
> // sign extend the physical address properly
> if (req->getPaddr() & PAddrUncachedBit40)
> req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
> else
> req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
335,339c337,341
< } else {
< // not a physical address: need to look up pte
< int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
< AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
< asn);
---
> } else {
> // not a physical address: need to look up pte
> int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
> PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
> asn);
341,344c343,346
< if (!pte) {
< misses++;
< return new ItbPageFault(req->getVaddr());
< }
---
> if (!pte) {
> misses++;
> return new ItbPageFault(req->getVaddr());
> }
346,348c348,350
< req->setPaddr((pte->ppn << AlphaISA::PageShift) +
< (AlphaISA::VAddr(req->getVaddr()).offset()
< & ~3));
---
> req->setPaddr((pte->ppn << PageShift) +
> (VAddr(req->getVaddr()).offset()
> & ~3));
350,356c352,358
< // check permissions for this access
< if (!(pte->xre &
< (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) {
< // instruction access fault
< acv++;
< return new ItbAcvFault(req->getVaddr());
< }
---
> // check permissions for this access
> if (!(pte->xre &
> (1 << ICM_CM(tc->readMiscReg(IPR_ICM))))) {
> // instruction access fault
> acv++;
> return new ItbAcvFault(req->getVaddr());
> }
358c360,361
< hits++;
---
> hits++;
> }
360d362
< }
362,364c364,366
< // check that the physical address is ok (catch bad physical addresses)
< if (req->getPaddr() & ~PAddrImplMask)
< return genMachineCheckFault();
---
> // check that the physical address is ok (catch bad physical addresses)
> if (req->getPaddr() & ~PAddrImplMask)
> return genMachineCheckFault();
366c368
< return checkCacheability(req);
---
> return checkCacheability(req);
368c370
< }
---
> }
370,376c372,378
< ///////////////////////////////////////////////////////////////////////
< //
< // Alpha DTB
< //
< AlphaDTB::AlphaDTB(const std::string &name, int size)
< : AlphaTLB(name, size)
< {}
---
> ///////////////////////////////////////////////////////////////////////
> //
> // Alpha DTB
> //
> DTB::DTB(const std::string &name, int size)
> : TLB(name, size)
> {}
378,384c380,386
< void
< AlphaDTB::regStats()
< {
< read_hits
< .name(name() + ".read_hits")
< .desc("DTB read hits")
< ;
---
> void
> DTB::regStats()
> {
> read_hits
> .name(name() + ".read_hits")
> .desc("DTB read hits")
> ;
386,389c388,391
< read_misses
< .name(name() + ".read_misses")
< .desc("DTB read misses")
< ;
---
> read_misses
> .name(name() + ".read_misses")
> .desc("DTB read misses")
> ;
391,394c393,396
< read_acv
< .name(name() + ".read_acv")
< .desc("DTB read access violations")
< ;
---
> read_acv
> .name(name() + ".read_acv")
> .desc("DTB read access violations")
> ;
396,399c398,401
< read_accesses
< .name(name() + ".read_accesses")
< .desc("DTB read accesses")
< ;
---
> read_accesses
> .name(name() + ".read_accesses")
> .desc("DTB read accesses")
> ;
401,404c403,406
< write_hits
< .name(name() + ".write_hits")
< .desc("DTB write hits")
< ;
---
> write_hits
> .name(name() + ".write_hits")
> .desc("DTB write hits")
> ;
406,409c408,411
< write_misses
< .name(name() + ".write_misses")
< .desc("DTB write misses")
< ;
---
> write_misses
> .name(name() + ".write_misses")
> .desc("DTB write misses")
> ;
411,414c413,416
< write_acv
< .name(name() + ".write_acv")
< .desc("DTB write access violations")
< ;
---
> write_acv
> .name(name() + ".write_acv")
> .desc("DTB write access violations")
> ;
416,419c418,421
< write_accesses
< .name(name() + ".write_accesses")
< .desc("DTB write accesses")
< ;
---
> write_accesses
> .name(name() + ".write_accesses")
> .desc("DTB write accesses")
> ;
421,424c423,426
< hits
< .name(name() + ".hits")
< .desc("DTB hits")
< ;
---
> hits
> .name(name() + ".hits")
> .desc("DTB hits")
> ;
426,429c428,431
< misses
< .name(name() + ".misses")
< .desc("DTB misses")
< ;
---
> misses
> .name(name() + ".misses")
> .desc("DTB misses")
> ;
431,434c433,436
< acv
< .name(name() + ".acv")
< .desc("DTB access violations")
< ;
---
> acv
> .name(name() + ".acv")
> .desc("DTB access violations")
> ;
436,439c438,441
< accesses
< .name(name() + ".accesses")
< .desc("DTB accesses")
< ;
---
> accesses
> .name(name() + ".accesses")
> .desc("DTB accesses")
> ;
441,445c443,447
< hits = read_hits + write_hits;
< misses = read_misses + write_misses;
< acv = read_acv + write_acv;
< accesses = read_accesses + write_accesses;
< }
---
> hits = read_hits + write_hits;
> misses = read_misses + write_misses;
> acv = read_acv + write_acv;
> accesses = read_accesses + write_accesses;
> }
447,450c449,452
< Fault
< AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
< {
< Addr pc = tc->readPC();
---
> Fault
> DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
> {
> Addr pc = tc->readPC();
452,453c454,455
< AlphaISA::mode_type mode =
< (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM));
---
> mode_type mode =
> (mode_type)DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM));
456,464c458,466
< /**
< * Check for alignment faults
< */
< if (req->getVaddr() & (req->getSize() - 1)) {
< DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
< req->getSize());
< uint64_t flags = write ? MM_STAT_WR_MASK : 0;
< return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
< }
---
> /**
> * Check for alignment faults
> */
> if (req->getVaddr() & (req->getSize() - 1)) {
> DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
> req->getSize());
> uint64_t flags = write ? MM_STAT_WR_MASK : 0;
> return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
> }
466,482c468,472
< if (pc & 0x1) {
< mode = (req->getFlags() & ALTMODE) ?
< (AlphaISA::mode_type)ALT_MODE_AM(
< tc->readMiscReg(AlphaISA::IPR_ALT_MODE))
< : AlphaISA::mode_kernel;
< }
<
< if (req->getFlags() & PHYSICAL) {
< req->setPaddr(req->getVaddr());
< } else {
< // verify that this is a good virtual address
< if (!validVirtualAddress(req->getVaddr())) {
< if (write) { write_acv++; } else { read_acv++; }
< uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
< MM_STAT_BAD_VA_MASK |
< MM_STAT_ACV_MASK;
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
---
> if (pc & 0x1) {
> mode = (req->getFlags() & ALTMODE) ?
> (mode_type)ALT_MODE_AM(
> tc->readMiscReg(IPR_ALT_MODE))
> : mode_kernel;
485c475,487
< // Check for "superpage" mapping
---
> if (req->getFlags() & PHYSICAL) {
> req->setPaddr(req->getVaddr());
> } else {
> // verify that this is a good virtual address
> if (!validVirtualAddress(req->getVaddr())) {
> if (write) { write_acv++; } else { read_acv++; }
> uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
> MM_STAT_BAD_VA_MASK |
> MM_STAT_ACV_MASK;
> return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
> }
>
> // Check for "superpage" mapping
487,488c489,490
< if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
< VAddrSpaceEV5(req->getVaddr()) == 2) {
---
> if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
> VAddrSpaceEV5(req->getVaddr()) == 2) {
490c492
< if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
---
> if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
493,500c495,502
< // only valid in kernel mode
< if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
< AlphaISA::mode_kernel) {
< if (write) { write_acv++; } else { read_acv++; }
< uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
< MM_STAT_ACV_MASK);
< return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
< }
---
> // only valid in kernel mode
> if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) !=
> mode_kernel) {
> if (write) { write_acv++; } else { read_acv++; }
> uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
> MM_STAT_ACV_MASK);
> return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
> }
502c504
< req->setPaddr(req->getVaddr() & PAddrImplMask);
---
> req->setPaddr(req->getVaddr() & PAddrImplMask);
505,509c507,511
< // sign extend the physical address properly
< if (req->getPaddr() & PAddrUncachedBit40)
< req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
< else
< req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
---
> // sign extend the physical address properly
> if (req->getPaddr() & PAddrUncachedBit40)
> req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
> else
> req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
512,516c514,518
< } else {
< if (write)
< write_accesses++;
< else
< read_accesses++;
---
> } else {
> if (write)
> write_accesses++;
> else
> read_accesses++;
518c520
< int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
---
> int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
520,522c522,524
< // not a physical address: need to look up pte
< AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
< asn);
---
> // not a physical address: need to look up pte
> PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
> asn);
524,534c526,536
< if (!pte) {
< // page fault
< if (write) { write_misses++; } else { read_misses++; }
< uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
< MM_STAT_DTB_MISS_MASK;
< return (req->getFlags() & VPTE) ?
< (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
< flags)) :
< (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
< flags));
< }
---
> if (!pte) {
> // page fault
> if (write) { write_misses++; } else { read_misses++; }
> uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
> MM_STAT_DTB_MISS_MASK;
> return (req->getFlags() & VPTE) ?
> (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
> flags)) :
> (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
> flags));
> }
536,537c538,539
< req->setPaddr((pte->ppn << AlphaISA::PageShift) +
< AlphaISA::VAddr(req->getVaddr()).offset());
---
> req->setPaddr((pte->ppn << PageShift) +
> VAddr(req->getVaddr()).offset());
539,546c541,567
< if (write) {
< if (!(pte->xwe & MODE2MASK(mode))) {
< // declare the instruction access fault
< write_acv++;
< uint64_t flags = MM_STAT_WR_MASK |
< MM_STAT_ACV_MASK |
< (pte->fonw ? MM_STAT_FONW_MASK : 0);
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
---
> if (write) {
> if (!(pte->xwe & MODE2MASK(mode))) {
> // declare the instruction access fault
> write_acv++;
> uint64_t flags = MM_STAT_WR_MASK |
> MM_STAT_ACV_MASK |
> (pte->fonw ? MM_STAT_FONW_MASK : 0);
> return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
> }
> if (pte->fonw) {
> write_acv++;
> uint64_t flags = MM_STAT_WR_MASK |
> MM_STAT_FONW_MASK;
> return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
> }
> } else {
> if (!(pte->xre & MODE2MASK(mode))) {
> read_acv++;
> uint64_t flags = MM_STAT_ACV_MASK |
> (pte->fonr ? MM_STAT_FONR_MASK : 0);
> return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
> }
> if (pte->fonr) {
> read_acv++;
> uint64_t flags = MM_STAT_FONR_MASK;
> return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
> }
548,565d568
< if (pte->fonw) {
< write_acv++;
< uint64_t flags = MM_STAT_WR_MASK |
< MM_STAT_FONW_MASK;
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
< }
< } else {
< if (!(pte->xre & MODE2MASK(mode))) {
< read_acv++;
< uint64_t flags = MM_STAT_ACV_MASK |
< (pte->fonr ? MM_STAT_FONR_MASK : 0);
< return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
< }
< if (pte->fonr) {
< read_acv++;
< uint64_t flags = MM_STAT_FONR_MASK;
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
< }
566a570,574
>
> if (write)
> write_hits++;
> else
> read_hits++;
569,572c577,581
< if (write)
< write_hits++;
< else
< read_hits++;
---
> // check that the physical address is ok (catch bad physical addresses)
> if (req->getPaddr() & ~PAddrImplMask)
> return genMachineCheckFault();
>
> return checkCacheability(req);
575,577c584,587
< // check that the physical address is ok (catch bad physical addresses)
< if (req->getPaddr() & ~PAddrImplMask)
< return genMachineCheckFault();
---
> PTE &
> TLB::index(bool advance)
> {
> PTE *pte = &table[nlu];
579,580c589,590
< return checkCacheability(req);
< }
---
> if (advance)
> nextnlu();
582,585c592,593
< AlphaISA::PTE &
< AlphaTLB::index(bool advance)
< {
< AlphaISA::PTE *pte = &table[nlu];
---
> return *pte;
> }
587,588c595
< if (advance)
< nextnlu();
---
> DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
590,591c597
< return *pte;
< }
---
> BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
593c599
< DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
---
> Param<int> size;
595c601
< BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
---
> END_DECLARE_SIM_OBJECT_PARAMS(ITB)
597c603
< Param<int> size;
---
> BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
599c605
< END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
---
> INIT_PARAM_DFLT(size, "TLB size", 48)
601c607
< BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
---
> END_INIT_SIM_OBJECT_PARAMS(ITB)
603d608
< INIT_PARAM_DFLT(size, "TLB size", 48)
605c610,613
< END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
---
> CREATE_SIM_OBJECT(ITB)
> {
> return new ITB(getInstanceName(), size);
> }
606a615
> REGISTER_SIM_OBJECT("AlphaITB", ITB)
608,611c617
< CREATE_SIM_OBJECT(AlphaITB)
< {
< return new AlphaITB(getInstanceName(), size);
< }
---
> BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
613c619
< REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
---
> Param<int> size;
615c621
< BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
---
> END_DECLARE_SIM_OBJECT_PARAMS(DTB)
617c623
< Param<int> size;
---
> BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
619c625
< END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
---
> INIT_PARAM_DFLT(size, "TLB size", 64)
621c627
< BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
---
> END_INIT_SIM_OBJECT_PARAMS(DTB)
623d628
< INIT_PARAM_DFLT(size, "TLB size", 64)
625c630,633
< END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
---
> CREATE_SIM_OBJECT(DTB)
> {
> return new DTB(getInstanceName(), size);
> }
627,630c635
<
< CREATE_SIM_OBJECT(AlphaDTB)
< {
< return new AlphaDTB(getInstanceName(), size);
---
> REGISTER_SIM_OBJECT("AlphaDTB", DTB)
632,634d636
<
< REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
<
< ///////////////////////////////////////////////////////////////////////
< //
< // Alpha TLB
< //
---
> namespace AlphaISA
> {
> ///////////////////////////////////////////////////////////////////////
> //
> // Alpha TLB
> //
54,55c56,57
< bool uncacheBit39 = false;
< bool uncacheBit40 = false;
---
> bool uncacheBit39 = false;
> bool uncacheBit40 = false;
60,65c62,67
< AlphaTLB::AlphaTLB(const string &name, int s)
< : SimObject(name), size(s), nlu(0)
< {
< table = new AlphaISA::PTE[size];
< memset(table, 0, sizeof(AlphaISA::PTE[size]));
< }
---
> TLB::TLB(const string &name, int s)
> : SimObject(name), size(s), nlu(0)
> {
> table = new PTE[size];
> memset(table, 0, sizeof(PTE[size]));
> }
67,71c69,73
< AlphaTLB::~AlphaTLB()
< {
< if (table)
< delete [] table;
< }
---
> TLB::~TLB()
> {
> if (table)
> delete [] table;
> }
73,78c75,80
< // look up an entry in the TLB
< AlphaISA::PTE *
< AlphaTLB::lookup(Addr vpn, uint8_t asn) const
< {
< // assume not found...
< AlphaISA::PTE *retval = NULL;
---
> // look up an entry in the TLB
> PTE *
> TLB::lookup(Addr vpn, uint8_t asn) const
> {
> // assume not found...
> PTE *retval = NULL;
80,89c82,91
< PageTable::const_iterator i = lookupTable.find(vpn);
< if (i != lookupTable.end()) {
< while (i->first == vpn) {
< int index = i->second;
< AlphaISA::PTE *pte = &table[index];
< assert(pte->valid);
< if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
< retval = pte;
< break;
< }
---
> PageTable::const_iterator i = lookupTable.find(vpn);
> if (i != lookupTable.end()) {
> while (i->first == vpn) {
> int index = i->second;
> PTE *pte = &table[index];
> assert(pte->valid);
> if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
> retval = pte;
> break;
> }
91c93,94
< ++i;
---
> ++i;
> }
92a96,99
>
> DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
> retval ? "hit" : "miss", retval ? retval->ppn : 0);
> return retval;
95,98d101
< DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
< retval ? "hit" : "miss", retval ? retval->ppn : 0);
< return retval;
< }
99a103,107
> Fault
> TLB::checkCacheability(RequestPtr &req)
> {
> // in Alpha, cacheability is controlled by upper-level bits of the
> // physical address
101,105c109,115
< Fault
< AlphaTLB::checkCacheability(RequestPtr &req)
< {
< // in Alpha, cacheability is controlled by upper-level bits of the
< // physical address
---
> /*
> * We support having the uncacheable bit in either bit 39 or bit 40.
> * The Turbolaser platform (and EV5) support having the bit in 39, but
> * Tsunami (which Linux assumes uses an EV6) generates accesses with
> * the bit in 40. So we must check for both, but we have debug flags
> * to catch a weird case where both are used, which shouldn't happen.
> */
107,113d116
< /*
< * We support having the uncacheable bit in either bit 39 or bit 40.
< * The Turbolaser platform (and EV5) support having the bit in 39, but
< * Tsunami (which Linux assumes uses an EV6) generates accesses with
< * the bit in 40. So we must check for both, but we have debug flags
< * to catch a weird case where both are used, which shouldn't happen.
< */
115d117
<
117c119
< if (req->getPaddr() & PAddrUncachedBit39) {
---
> if (req->getPaddr() & PAddrUncachedBit39) {
119c121
< if (req->getPaddr() & PAddrUncachedBit43) {
---
> if (req->getPaddr() & PAddrUncachedBit43) {
121,126c123,128
< // IPR memory space not implemented
< if (PAddrIprSpace(req->getPaddr())) {
< return new UnimpFault("IPR memory space not implemented!");
< } else {
< // mark request as uncacheable
< req->setFlags(req->getFlags() | UNCACHEABLE);
---
> // IPR memory space not implemented
> if (PAddrIprSpace(req->getPaddr())) {
> return new UnimpFault("IPR memory space not implemented!");
> } else {
> // mark request as uncacheable
> req->setFlags(req->getFlags() | UNCACHEABLE);
129,130c131,132
< // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
< req->setPaddr(req->getPaddr() & PAddrUncachedMask);
---
> // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
> req->setPaddr(req->getPaddr() & PAddrUncachedMask);
131a134
> }
132a136
> return NoFault;
134,135d137
< return NoFault;
< }
138,145c140,147
< // insert a new TLB entry
< void
< AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte)
< {
< AlphaISA::VAddr vaddr = addr;
< if (table[nlu].valid) {
< Addr oldvpn = table[nlu].tag;
< PageTable::iterator i = lookupTable.find(oldvpn);
---
> // insert a new TLB entry
> void
> TLB::insert(Addr addr, PTE &pte)
> {
> VAddr vaddr = addr;
> if (table[nlu].valid) {
> Addr oldvpn = table[nlu].tag;
> PageTable::iterator i = lookupTable.find(oldvpn);
147,152c149
< if (i == lookupTable.end())
< panic("TLB entry not found in lookupTable");
<
< int index;
< while ((index = i->second) != nlu) {
< if (table[index].tag != oldvpn)
---
> if (i == lookupTable.end())
155,156c152,155
< ++i;
< }
---
> int index;
> while ((index = i->second) != nlu) {
> if (table[index].tag != oldvpn)
> panic("TLB entry not found in lookupTable");
158c157,158
< DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
---
> ++i;
> }
160,161c160
< lookupTable.erase(i);
< }
---
> DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
163c162,163
< DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
---
> lookupTable.erase(i);
> }
165,167c165
< table[nlu] = pte;
< table[nlu].tag = vaddr.vpn();
< table[nlu].valid = true;
---
> DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn);
169,171c167,169
< lookupTable.insert(make_pair(vaddr.vpn(), nlu));
< nextnlu();
< }
---
> table[nlu] = pte;
> table[nlu].tag = vaddr.vpn();
> table[nlu].valid = true;
173,180c171,173
< void
< AlphaTLB::flushAll()
< {
< DPRINTF(TLB, "flushAll\n");
< memset(table, 0, sizeof(AlphaISA::PTE[size]));
< lookupTable.clear();
< nlu = 0;
< }
---
> lookupTable.insert(make_pair(vaddr.vpn(), nlu));
> nextnlu();
> }
182,190c175,182
< void
< AlphaTLB::flushProcesses()
< {
< PageTable::iterator i = lookupTable.begin();
< PageTable::iterator end = lookupTable.end();
< while (i != end) {
< int index = i->second;
< AlphaISA::PTE *pte = &table[index];
< assert(pte->valid);
---
> void
> TLB::flushAll()
> {
> DPRINTF(TLB, "flushAll\n");
> memset(table, 0, sizeof(PTE[size]));
> lookupTable.clear();
> nlu = 0;
> }
192,195c184,192
< // we can't increment i after we erase it, so save a copy and
< // increment it to get the next entry now
< PageTable::iterator cur = i;
< ++i;
---
> void
> TLB::flushProcesses()
> {
> PageTable::iterator i = lookupTable.begin();
> PageTable::iterator end = lookupTable.end();
> while (i != end) {
> int index = i->second;
> PTE *pte = &table[index];
> assert(pte->valid);
197,200c194,203
< if (!pte->asma) {
< DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
< pte->valid = false;
< lookupTable.erase(cur);
---
> // we can't increment i after we erase it, so save a copy and
> // increment it to get the next entry now
> PageTable::iterator cur = i;
> ++i;
>
> if (!pte->asma) {
> DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
> pte->valid = false;
> lookupTable.erase(cur);
> }
203d205
< }
205,208c207,210
< void
< AlphaTLB::flushAddr(Addr addr, uint8_t asn)
< {
< AlphaISA::VAddr vaddr = addr;
---
> void
> TLB::flushAddr(Addr addr, uint8_t asn)
> {
> VAddr vaddr = addr;
210,212c212,214
< PageTable::iterator i = lookupTable.find(vaddr.vpn());
< if (i == lookupTable.end())
< return;
---
> PageTable::iterator i = lookupTable.find(vaddr.vpn());
> if (i == lookupTable.end())
> return;
214,217c216,219
< while (i->first == vaddr.vpn()) {
< int index = i->second;
< AlphaISA::PTE *pte = &table[index];
< assert(pte->valid);
---
> while (i->first == vaddr.vpn()) {
> int index = i->second;
> PTE *pte = &table[index];
> assert(pte->valid);
219,221c221,223
< if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
< DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
< pte->ppn);
---
> if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) {
> DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
> pte->ppn);
223,224c225,226
< // invalidate this entry
< pte->valid = false;
---
> // invalidate this entry
> pte->valid = false;
226,227c228,229
< lookupTable.erase(i);
< }
---
> lookupTable.erase(i);
> }
229c231,232
< ++i;
---
> ++i;
> }
231d233
< }
234,238c236,240
< void
< AlphaTLB::serialize(ostream &os)
< {
< SERIALIZE_SCALAR(size);
< SERIALIZE_SCALAR(nlu);
---
> void
> TLB::serialize(ostream &os)
> {
> SERIALIZE_SCALAR(size);
> SERIALIZE_SCALAR(nlu);
240,242c242,245
< for (int i = 0; i < size; i++) {
< nameOut(os, csprintf("%s.PTE%d", name(), i));
< table[i].serialize(os);
---
> for (int i = 0; i < size; i++) {
> nameOut(os, csprintf("%s.PTE%d", name(), i));
> table[i].serialize(os);
> }
244d246
< }
246,250c248,252
< void
< AlphaTLB::unserialize(Checkpoint *cp, const string §ion)
< {
< UNSERIALIZE_SCALAR(size);
< UNSERIALIZE_SCALAR(nlu);
---
> void
> TLB::unserialize(Checkpoint *cp, const string §ion)
> {
> UNSERIALIZE_SCALAR(size);
> UNSERIALIZE_SCALAR(nlu);
252,255c254,258
< for (int i = 0; i < size; i++) {
< table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
< if (table[i].valid) {
< lookupTable.insert(make_pair(table[i].tag, i));
---
> for (int i = 0; i < size; i++) {
> table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
> if (table[i].valid) {
> lookupTable.insert(make_pair(table[i].tag, i));
> }
258d260
< }
261,267c263,269
< ///////////////////////////////////////////////////////////////////////
< //
< // Alpha ITB
< //
< AlphaITB::AlphaITB(const std::string &name, int size)
< : AlphaTLB(name, size)
< {}
---
> ///////////////////////////////////////////////////////////////////////
> //
> // Alpha ITB
> //
> ITB::ITB(const std::string &name, int size)
> : TLB(name, size)
> {}
270,284c272,286
< void
< AlphaITB::regStats()
< {
< hits
< .name(name() + ".hits")
< .desc("ITB hits");
< misses
< .name(name() + ".misses")
< .desc("ITB misses");
< acv
< .name(name() + ".acv")
< .desc("ITB acv");
< accesses
< .name(name() + ".accesses")
< .desc("ITB accesses");
---
> void
> ITB::regStats()
> {
> hits
> .name(name() + ".hits")
> .desc("ITB hits");
> misses
> .name(name() + ".misses")
> .desc("ITB misses");
> acv
> .name(name() + ".acv")
> .desc("ITB acv");
> accesses
> .name(name() + ".accesses")
> .desc("ITB accesses");
286,297c288
< accesses = hits + misses;
< }
<
<
< Fault
< AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const
< {
< if (AlphaISA::PcPAL(req->getVaddr())) {
< // strip off PAL PC marker (lsb is 1)
< req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
< hits++;
< return NoFault;
---
> accesses = hits + misses;
300,306c291,299
< if (req->getFlags() & PHYSICAL) {
< req->setPaddr(req->getVaddr());
< } else {
< // verify that this is a good virtual address
< if (!validVirtualAddress(req->getVaddr())) {
< acv++;
< return new ItbAcvFault(req->getVaddr());
---
>
> Fault
> ITB::translate(RequestPtr &req, ThreadContext *tc) const
> {
> if (PcPAL(req->getVaddr())) {
> // strip off PAL PC marker (lsb is 1)
> req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
> hits++;
> return NoFault;
308a302,309
> if (req->getFlags() & PHYSICAL) {
> req->setPaddr(req->getVaddr());
> } else {
> // verify that this is a good virtual address
> if (!validVirtualAddress(req->getVaddr())) {
> acv++;
> return new ItbAcvFault(req->getVaddr());
> }
310,311c311,313
< // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
< // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
---
>
> // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
> // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
313,314c315,316
< if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
< VAddrSpaceEV5(req->getVaddr()) == 2) {
---
> if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
> VAddrSpaceEV5(req->getVaddr()) == 2) {
316c318
< if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
---
> if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
318,323c320,325
< // only valid in kernel mode
< if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) !=
< AlphaISA::mode_kernel) {
< acv++;
< return new ItbAcvFault(req->getVaddr());
< }
---
> // only valid in kernel mode
> if (ICM_CM(tc->readMiscReg(IPR_ICM)) !=
> mode_kernel) {
> acv++;
> return new ItbAcvFault(req->getVaddr());
> }
325c327
< req->setPaddr(req->getVaddr() & PAddrImplMask);
---
> req->setPaddr(req->getVaddr() & PAddrImplMask);
328,332c330,334
< // sign extend the physical address properly
< if (req->getPaddr() & PAddrUncachedBit40)
< req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
< else
< req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
---
> // sign extend the physical address properly
> if (req->getPaddr() & PAddrUncachedBit40)
> req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
> else
> req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
335,339c337,341
< } else {
< // not a physical address: need to look up pte
< int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
< AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
< asn);
---
> } else {
> // not a physical address: need to look up pte
> int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
> PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
> asn);
341,344c343,346
< if (!pte) {
< misses++;
< return new ItbPageFault(req->getVaddr());
< }
---
> if (!pte) {
> misses++;
> return new ItbPageFault(req->getVaddr());
> }
346,348c348,350
< req->setPaddr((pte->ppn << AlphaISA::PageShift) +
< (AlphaISA::VAddr(req->getVaddr()).offset()
< & ~3));
---
> req->setPaddr((pte->ppn << PageShift) +
> (VAddr(req->getVaddr()).offset()
> & ~3));
350,356c352,358
< // check permissions for this access
< if (!(pte->xre &
< (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) {
< // instruction access fault
< acv++;
< return new ItbAcvFault(req->getVaddr());
< }
---
> // check permissions for this access
> if (!(pte->xre &
> (1 << ICM_CM(tc->readMiscReg(IPR_ICM))))) {
> // instruction access fault
> acv++;
> return new ItbAcvFault(req->getVaddr());
> }
358c360,361
< hits++;
---
> hits++;
> }
360d362
< }
362,364c364,366
< // check that the physical address is ok (catch bad physical addresses)
< if (req->getPaddr() & ~PAddrImplMask)
< return genMachineCheckFault();
---
> // check that the physical address is ok (catch bad physical addresses)
> if (req->getPaddr() & ~PAddrImplMask)
> return genMachineCheckFault();
366c368
< return checkCacheability(req);
---
> return checkCacheability(req);
368c370
< }
---
> }
370,376c372,378
< ///////////////////////////////////////////////////////////////////////
< //
< // Alpha DTB
< //
< AlphaDTB::AlphaDTB(const std::string &name, int size)
< : AlphaTLB(name, size)
< {}
---
> ///////////////////////////////////////////////////////////////////////
> //
> // Alpha DTB
> //
> DTB::DTB(const std::string &name, int size)
> : TLB(name, size)
> {}
378,384c380,386
< void
< AlphaDTB::regStats()
< {
< read_hits
< .name(name() + ".read_hits")
< .desc("DTB read hits")
< ;
---
> void
> DTB::regStats()
> {
> read_hits
> .name(name() + ".read_hits")
> .desc("DTB read hits")
> ;
386,389c388,391
< read_misses
< .name(name() + ".read_misses")
< .desc("DTB read misses")
< ;
---
> read_misses
> .name(name() + ".read_misses")
> .desc("DTB read misses")
> ;
391,394c393,396
< read_acv
< .name(name() + ".read_acv")
< .desc("DTB read access violations")
< ;
---
> read_acv
> .name(name() + ".read_acv")
> .desc("DTB read access violations")
> ;
396,399c398,401
< read_accesses
< .name(name() + ".read_accesses")
< .desc("DTB read accesses")
< ;
---
> read_accesses
> .name(name() + ".read_accesses")
> .desc("DTB read accesses")
> ;
401,404c403,406
< write_hits
< .name(name() + ".write_hits")
< .desc("DTB write hits")
< ;
---
> write_hits
> .name(name() + ".write_hits")
> .desc("DTB write hits")
> ;
406,409c408,411
< write_misses
< .name(name() + ".write_misses")
< .desc("DTB write misses")
< ;
---
> write_misses
> .name(name() + ".write_misses")
> .desc("DTB write misses")
> ;
411,414c413,416
< write_acv
< .name(name() + ".write_acv")
< .desc("DTB write access violations")
< ;
---
> write_acv
> .name(name() + ".write_acv")
> .desc("DTB write access violations")
> ;
416,419c418,421
< write_accesses
< .name(name() + ".write_accesses")
< .desc("DTB write accesses")
< ;
---
> write_accesses
> .name(name() + ".write_accesses")
> .desc("DTB write accesses")
> ;
421,424c423,426
< hits
< .name(name() + ".hits")
< .desc("DTB hits")
< ;
---
> hits
> .name(name() + ".hits")
> .desc("DTB hits")
> ;
426,429c428,431
< misses
< .name(name() + ".misses")
< .desc("DTB misses")
< ;
---
> misses
> .name(name() + ".misses")
> .desc("DTB misses")
> ;
431,434c433,436
< acv
< .name(name() + ".acv")
< .desc("DTB access violations")
< ;
---
> acv
> .name(name() + ".acv")
> .desc("DTB access violations")
> ;
436,439c438,441
< accesses
< .name(name() + ".accesses")
< .desc("DTB accesses")
< ;
---
> accesses
> .name(name() + ".accesses")
> .desc("DTB accesses")
> ;
441,445c443,447
< hits = read_hits + write_hits;
< misses = read_misses + write_misses;
< acv = read_acv + write_acv;
< accesses = read_accesses + write_accesses;
< }
---
> hits = read_hits + write_hits;
> misses = read_misses + write_misses;
> acv = read_acv + write_acv;
> accesses = read_accesses + write_accesses;
> }
447,450c449,452
< Fault
< AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
< {
< Addr pc = tc->readPC();
---
> Fault
> DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
> {
> Addr pc = tc->readPC();
452,453c454,455
< AlphaISA::mode_type mode =
< (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM));
---
> mode_type mode =
> (mode_type)DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM));
456,464c458,466
< /**
< * Check for alignment faults
< */
< if (req->getVaddr() & (req->getSize() - 1)) {
< DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
< req->getSize());
< uint64_t flags = write ? MM_STAT_WR_MASK : 0;
< return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
< }
---
> /**
> * Check for alignment faults
> */
> if (req->getVaddr() & (req->getSize() - 1)) {
> DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
> req->getSize());
> uint64_t flags = write ? MM_STAT_WR_MASK : 0;
> return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
> }
466,482c468,472
< if (pc & 0x1) {
< mode = (req->getFlags() & ALTMODE) ?
< (AlphaISA::mode_type)ALT_MODE_AM(
< tc->readMiscReg(AlphaISA::IPR_ALT_MODE))
< : AlphaISA::mode_kernel;
< }
<
< if (req->getFlags() & PHYSICAL) {
< req->setPaddr(req->getVaddr());
< } else {
< // verify that this is a good virtual address
< if (!validVirtualAddress(req->getVaddr())) {
< if (write) { write_acv++; } else { read_acv++; }
< uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
< MM_STAT_BAD_VA_MASK |
< MM_STAT_ACV_MASK;
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
---
> if (pc & 0x1) {
> mode = (req->getFlags() & ALTMODE) ?
> (mode_type)ALT_MODE_AM(
> tc->readMiscReg(IPR_ALT_MODE))
> : mode_kernel;
485c475,487
< // Check for "superpage" mapping
---
> if (req->getFlags() & PHYSICAL) {
> req->setPaddr(req->getVaddr());
> } else {
> // verify that this is a good virtual address
> if (!validVirtualAddress(req->getVaddr())) {
> if (write) { write_acv++; } else { read_acv++; }
> uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
> MM_STAT_BAD_VA_MASK |
> MM_STAT_ACV_MASK;
> return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
> }
>
> // Check for "superpage" mapping
487,488c489,490
< if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
< VAddrSpaceEV5(req->getVaddr()) == 2) {
---
> if ((MCSR_SP(tc->readMiscReg(IPR_MCSR)) & 2) &&
> VAddrSpaceEV5(req->getVaddr()) == 2) {
490c492
< if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
---
> if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
493,500c495,502
< // only valid in kernel mode
< if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
< AlphaISA::mode_kernel) {
< if (write) { write_acv++; } else { read_acv++; }
< uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
< MM_STAT_ACV_MASK);
< return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
< }
---
> // only valid in kernel mode
> if (DTB_CM_CM(tc->readMiscReg(IPR_DTB_CM)) !=
> mode_kernel) {
> if (write) { write_acv++; } else { read_acv++; }
> uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
> MM_STAT_ACV_MASK);
> return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
> }
502c504
< req->setPaddr(req->getVaddr() & PAddrImplMask);
---
> req->setPaddr(req->getVaddr() & PAddrImplMask);
505,509c507,511
< // sign extend the physical address properly
< if (req->getPaddr() & PAddrUncachedBit40)
< req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
< else
< req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
---
> // sign extend the physical address properly
> if (req->getPaddr() & PAddrUncachedBit40)
> req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
> else
> req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
512,516c514,518
< } else {
< if (write)
< write_accesses++;
< else
< read_accesses++;
---
> } else {
> if (write)
> write_accesses++;
> else
> read_accesses++;
518c520
< int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
---
> int asn = DTB_ASN_ASN(tc->readMiscReg(IPR_DTB_ASN));
520,522c522,524
< // not a physical address: need to look up pte
< AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
< asn);
---
> // not a physical address: need to look up pte
> PTE *pte = lookup(VAddr(req->getVaddr()).vpn(),
> asn);
524,534c526,536
< if (!pte) {
< // page fault
< if (write) { write_misses++; } else { read_misses++; }
< uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
< MM_STAT_DTB_MISS_MASK;
< return (req->getFlags() & VPTE) ?
< (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
< flags)) :
< (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
< flags));
< }
---
> if (!pte) {
> // page fault
> if (write) { write_misses++; } else { read_misses++; }
> uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
> MM_STAT_DTB_MISS_MASK;
> return (req->getFlags() & VPTE) ?
> (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
> flags)) :
> (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
> flags));
> }
536,537c538,539
< req->setPaddr((pte->ppn << AlphaISA::PageShift) +
< AlphaISA::VAddr(req->getVaddr()).offset());
---
> req->setPaddr((pte->ppn << PageShift) +
> VAddr(req->getVaddr()).offset());
539,546c541,567
< if (write) {
< if (!(pte->xwe & MODE2MASK(mode))) {
< // declare the instruction access fault
< write_acv++;
< uint64_t flags = MM_STAT_WR_MASK |
< MM_STAT_ACV_MASK |
< (pte->fonw ? MM_STAT_FONW_MASK : 0);
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
---
> if (write) {
> if (!(pte->xwe & MODE2MASK(mode))) {
> // declare the instruction access fault
> write_acv++;
> uint64_t flags = MM_STAT_WR_MASK |
> MM_STAT_ACV_MASK |
> (pte->fonw ? MM_STAT_FONW_MASK : 0);
> return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
> }
> if (pte->fonw) {
> write_acv++;
> uint64_t flags = MM_STAT_WR_MASK |
> MM_STAT_FONW_MASK;
> return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
> }
> } else {
> if (!(pte->xre & MODE2MASK(mode))) {
> read_acv++;
> uint64_t flags = MM_STAT_ACV_MASK |
> (pte->fonr ? MM_STAT_FONR_MASK : 0);
> return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
> }
> if (pte->fonr) {
> read_acv++;
> uint64_t flags = MM_STAT_FONR_MASK;
> return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
> }
548,565d568
< if (pte->fonw) {
< write_acv++;
< uint64_t flags = MM_STAT_WR_MASK |
< MM_STAT_FONW_MASK;
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
< }
< } else {
< if (!(pte->xre & MODE2MASK(mode))) {
< read_acv++;
< uint64_t flags = MM_STAT_ACV_MASK |
< (pte->fonr ? MM_STAT_FONR_MASK : 0);
< return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
< }
< if (pte->fonr) {
< read_acv++;
< uint64_t flags = MM_STAT_FONR_MASK;
< return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
< }
566a570,574
>
> if (write)
> write_hits++;
> else
> read_hits++;
569,572c577,581
< if (write)
< write_hits++;
< else
< read_hits++;
---
> // check that the physical address is ok (catch bad physical addresses)
> if (req->getPaddr() & ~PAddrImplMask)
> return genMachineCheckFault();
>
> return checkCacheability(req);
575,577c584,587
< // check that the physical address is ok (catch bad physical addresses)
< if (req->getPaddr() & ~PAddrImplMask)
< return genMachineCheckFault();
---
> PTE &
> TLB::index(bool advance)
> {
> PTE *pte = &table[nlu];
579,580c589,590
< return checkCacheability(req);
< }
---
> if (advance)
> nextnlu();
582,585c592,593
< AlphaISA::PTE &
< AlphaTLB::index(bool advance)
< {
< AlphaISA::PTE *pte = &table[nlu];
---
> return *pte;
> }
587,588c595
< if (advance)
< nextnlu();
---
> DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
590,591c597
< return *pte;
< }
---
> BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
593c599
< DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
---
> Param<int> size;
595c601
< BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
---
> END_DECLARE_SIM_OBJECT_PARAMS(ITB)
597c603
< Param<int> size;
---
> BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
599c605
< END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
---
> INIT_PARAM_DFLT(size, "TLB size", 48)
601c607
< BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
---
> END_INIT_SIM_OBJECT_PARAMS(ITB)
603d608
< INIT_PARAM_DFLT(size, "TLB size", 48)
605c610,613
< END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
---
> CREATE_SIM_OBJECT(ITB)
> {
> return new ITB(getInstanceName(), size);
> }
606a615
> REGISTER_SIM_OBJECT("AlphaITB", ITB)
608,611c617
< CREATE_SIM_OBJECT(AlphaITB)
< {
< return new AlphaITB(getInstanceName(), size);
< }
---
> BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
613c619
< REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
---
> Param<int> size;
615c621
< BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
---
> END_DECLARE_SIM_OBJECT_PARAMS(DTB)
617c623
< Param<int> size;
---
> BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
619c625
< END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
---
> INIT_PARAM_DFLT(size, "TLB size", 64)
621c627
< BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
---
> END_INIT_SIM_OBJECT_PARAMS(DTB)
623d628
< INIT_PARAM_DFLT(size, "TLB size", 64)
625c630,633
< END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
---
> CREATE_SIM_OBJECT(DTB)
> {
> return new DTB(getInstanceName(), size);
> }
627,630c635
<
< CREATE_SIM_OBJECT(AlphaDTB)
< {
< return new AlphaDTB(getInstanceName(), size);
---
> REGISTER_SIM_OBJECT("AlphaDTB", DTB)
632,634d636
<
< REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
<